Taiwan Semiconductor Manufacturing Comp. Ltd.

Texas Instruments Corporation

Anthony Yen

Shinn-Sheng Yu

Jeng-Horng Chen

Yen-Cheng Lu

Chih-Tsung Shih

Hsin-Chang Lee

Chia-Jen Chen

Shang-Chieh Chien

Yun-Yue Lin

Chia-Chen Chen

Pei-Cheng Hsu

Shu-Hao Chang

Ta-Cheng Lien

Chih-Cheng Lin

Jui-Ching Wu

Ming-Chin Chien

Sheng-Chi Chin

Chi-Lun Lu

Norman Chen

Chin-Hsiang Lin

Ming-Feng Shieh

Chia-Hao Hsu

Hung-Chang Hsieh

Jeff J Xu

Tsiao-Chen Wu

Kuo-Chang Kau

Kevin Huang

Tao-Min Huang

Hsuan-Chen Chen

Syun-Ming Jang Jang

Clement Hsingjen Wann

Li-Jui Chen

Chung-Ju Lee

Po-Chung Cheng

Shao-Ming Yu

Chang-Yun Chang

Tzung-Chi Fu

Chun-Lin Louis Chang

Bo-Tsun Liu

Ting-Hao Hsu

Yao-Ching Ku

Shang-Ying Wu

Shun-Der Wu

Tien-Hsi Lee

Li-Kai Cheng

Chen-Hua Douglas Yu

Shih-Ming Chang

Tsai-Sheng Gau

Chia-Hao Yu

Burn Jeng Lin

Tsu Shih

Wen-Chuan Wang

Tsung-Min Huang

Wei-Jen Lo

Wei-Hung Liu

Ming-Jiun Yao

Hsuan-I Wang

Wei-Shiuan Chen

Yeh Lee-Chih

Mark Chien

Chia-Shiung Tsai

Ru-Gun Liu

Hun-Jan Tao

Ming-Ching Chang

Hua-Tai Lin

Chih-Ming Ke

Hsin-Chieh Yao

Jaw-Jung Shin

San-De Tzu

Jih-Churng Twu

Kuan-Wen Lin

Ching-Fang Yu

Tzu-Li Lee

Chieh-Jen Cheng

Wei-Chih Lai

Ching-Wei Shen

Ying-Yu Chen

Cesar M Garza

Yih-Chen Su

Lee-Chih Yeh

Chia-Chun Chung

Yi-Ling Hsieh

Zhiliu Ma

Chen-Hao Hsieh

Chia-Tsung Shih

Pei-Chung Hsu

Huan-Tai Lin

Tsai-Sheng Giau

Shih-Ying Chen

Jih-Chuyng Twu

Chung Hsing Chang

An apparatus includes a vacuum chamber, a reflective optical element arranged in the vacuum chamber and configured to reflect an extreme ultra-violet (EUV) light, and a cleaning module positioned in the vacuum chamber. the cleaning module is operable to provide a mitigation gas flowing towards the reflective optical element and provide a hydrogen-containing gas flowing towards the reflective optical element. The mitigation gas mitigates, by chemical reaction, contamination of the reflective optical element.

Mask cleaning

A lithography system includes a first load lock chamber configured to receive a mask, a cleaning module configured to clean the mask, a second load lock chamber configured to receive a wafer, an exposure module configured to expose the wafer to a light source through use of the cleaned mask. A direct path is provided between the first load lock chamber and the exposure module allowing the first load lock chamber to directly couple to the exposure module without through the cleaning module.

The present disclosure provides a lithography system. The lithography system includes an exposing module configured to perform a lithography exposing process using a mask secured on a mask stage; and a cleaning module integrated in the exposing module and designed to clean at least one of the mask and the mask stage using an attraction mechanism.

Lithography system with an embedded cleaning module

A lithography system includes a load lock chamber comprising an opening configured to receive a mask, an exposure module configured to expose a semiconductor wafer to a light source through use of the mask, and a cleaning module embedded inside the lithography tool, the cleaning module being configured to clean carbon particles from the mask.

A method of performing a lithography process includes receiving a lithography mask and performing overlay measurement. The lithography mask includes a substrate that contains a low thermal expansion material (LTEM); a reflective structure over a first side of the substrate; an absorber layer over the reflective structure and containing one or more first overlay marks; and a conductive layer over a second side of the substrate and containing one or more second overlay marks. The second side is opposite the first side. The overlay measurement includes using the one or more first overlay marks in an extreme ultraviolet (EUV) lithography process or using the one or more second overlay marks in a non-EUV lithography process.

Lithography mask with both transmission-type and reflective-type overlay marks and method of fabricating the same

A single-shot metrology for direct inspection of an entirety of the interior of an EUV vessel is provided. An EUV vessel including an inspection tool integrated with the EUV vessel is provided. During an inspection process, the inspection tool is moved into a primary focus region of the EUV vessel. While the inspection tool is disposed at the primary focus region and while providing a substantially uniform and constant light level to an interior of the EUV vessel by way of an illuminator, a panoramic image of an interior of the EUV vessel is captured by way of a single-shot of the inspection tool. Thereafter, a level of tin contamination on a plurality of components of the EUV vessel is quantified based on the panoramic image of the interior of the EUV vessel. The quantified level of contamination is compared to a KPI, and an OCAP may be implemented.

EUV vessel inspection method and related system

Various methods are disclosed herein for reducing (or eliminating) printability of mask defects during lithography processes. An exemplary method includes performing a first lithography exposing process and a second lithography exposing process using a mask to respectively image a first set of polygons oriented substantially along a first direction and a second set of polygons oriented substantially along a second direction on a target. During the first lithography exposing process, a phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the first direction and a third direction that is different than the first direction. During the second lithography exposing process, the phase distribution of light diffracted from the mask is dynamically modulated to defocus any mask defect oriented at least partially along both the second direction and a fourth direction that is different than the third direction.

Method to mitigate defect printability for ID pattern

The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.

Mask with multilayer structure and manufacturing method by using the same

A lithography system includes a radiation source configured to generate an extreme ultraviolet (EUV) light. The lithography system includes a mask that defines one or more features of an integrated circuit (IC). The lithography system includes an illuminator configured to direct the EUV light onto the mask. The mask diffracts the EUV light into a 0-th order ray and a plurality of higher order rays. The lithography system includes a wafer stage configured to secure a wafer that is to be patterned according to the one or more features defined by the mask. The lithography system includes a pupil phase modulator positioned in a pupil plane that is located between the mask and the wafer stage. The pupil phase modulator is configured to change a phase of the 0-th order ray.

Extreme ultraviolet lithography system, device, and method for printing low pattern density features

Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.

System and method for performing lithography process in semiconductor device fabrication

An extreme ultraviolet lithography method is disclosed. In an example, the EUVL method includes forming a resist layer on a substrate; performing a first exposure process to image a first pattern of a first sub-region of a first mask to the resist layer; performing a second exposure process to image a second pattern of a second sub-region of the first mask to the resist layer; and performing a third exposure process to image a third pattern of a first sub-region of a second mask to the resist layer. The second and third patterns are identical to the first pattern. The first, second and third exposure processes collectively form a latent image of the first pattern on the resist layer.

Lithography method with reduced impacts of mask defects

The present disclosure provides a method in accordance with some embodiments. A wafer is grinded from a back side. The wafer is inserted into an opening defined by a frame holder. The frame holder is attached to a carrier through a temporary layer. A front side of the wafer is attached to the temporary layer. Thereafter, the wafer is etched from the back side until the wafer reaches a predetermined thickness. Thereafter, the frame holder and the wafer therein are separated from the temporary layer and the carrier.

Pellicle for EUV mask and fabrication thereof

A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Pellicle fabrication methods and structures thereof

Growing community of inventors

Hsinchu, Taiwan

Anthony Yen