Intel Corporation

Anthony Wojciechowski

Michael Mishaeli

Tsvika Kurts

Beeman C Strong

Michael W Chynoweth

Rajshree Chabukswar

Itamar S Kazachinsky

Richard B O'Connor

Avner Lottem

Vikas R Vasisht

Jonathan D Combs

Kameswar Subramaniam

A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets may include four additional packets for processor event tracing including: a dormant state request packet, a code execution stop packet, a dormant state entry packet, and a dormant state exit packet.

Processor core power event tracing

A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.

Programmable logic array and read-only memory area reduction using context-sensitive logic for data space manipulation

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Austin, TX, United States of America

Anthony Wojciechowski