Agere Systems Inc.

Cabletron Systems, Inc.

Anthony W Seaman

Tony S El-Kik

William P Cornelius

Parag Parikh

Stefan Allen Siegel

Robert J Baumert

Stephen A Masnica

Sherre M Staves

A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Signal buffering and retiming circuit for multiple memories

A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations

A switch apparatus for optimizing the transfer of data packets between a plurality of local area networks (LANs). Apparatus of the present invention are comprised of multiple independent controllers, e.g., a receive controller and a transmit controller, which share common resources including a first memory (a packet memory) which stores the data packets, a second memory (a descriptor memory) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers). The independent controllers operate essentially concurrently for most tasks while interleaving their use of the shared resources. Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).

Method and apparatus for optimizing the transfer of data packets between

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Bethlehem, PA, United States of America

Anthony W Seaman