Intel Corporation

Resonance Semiconductor Corporation

Apple Inc.

Intel IP Corporation

Anthony Tsangaropoulos

Prasanna Desai

Itzik Shahar

Dongsheng Bi

Jinyong Lee

Brian J Sublett

Assaf Gurevitz

Ilan Sutskover

Oren Kaidar

L Richard Carley

Sumit Verma

Mariam Motamed

Dor Chay

Divyaprakash P Bhojkumar

Ronen Kronfeld

Yuwei Zhang

David Francois Guillou

Sharon Heruti

Thomas W Brown

Amith Vikram Chincholi

Reuven Lavie

Esa Tarvainen

Chen Meng

An apparatus of user equipment (UE) includes processing circuitry coupled to a memory, where to configure the UE for dynamic transmit power adjustment, the processing circuitry is to decode baseband configuration information received from a base station. The baseband configuration information including at least a modulation and coding scheme (MCS), resource block (RB) allocation, and carrier assignment for uplink (UL) transmission and downlink (DL) reception. A communication mode is selected based on the baseband configuration information. An additional maximum power reduction (A-MPR) is determined based on the baseband configuration information and the selected communication mode. UL data is encoded for transmission to the base station via the selected communication mode and using transmit power adjusted based on the determined A-MPR. New signaling enhancements between the UE and the network (on a Uu interface) and between two UEs (on a PC5 sidelink interface) are also disclosed.

Dynamic transmit power adjustment

In one embodiment, an apparatus of a wireless communication device includes control circuitry to cause receiver circuitry of the wireless communication device to switch between an on-mode and an off-mode. The apparatus also includes synchronizing circuitry to: perform a correlation on signals of a packet received by the receiver circuitry when in the on-mode to detect a pattern in the received signals, and cause the control circuitry to hold the receiver circuitry in the on-mode based on detection of the pattern in the received signals. The apparatus further includes demodulation circuitry to process additional signals of the packet received by the receiver circuitry when held in the on-mode.

Time slotted scan receiver

An arrangement for detection of multiple signals concurrently is disclosed. The arrangement includes a demodulator component, a mixer and a detector. The demodulator component is configured to demodulate or obtain one or more components from a received signal. The mixer is configured to mix the one or more components into a folded signal using a plurality of varied local oscillator (LO) signals. The detector is configured to identify a valid signal within the folded signal and to initiate a response for the identified valid signal.

Arrangement for concurrent detection of signals in a receiver

Described herein are technologies related to an implementation of interference mitigation in a receiver of a portable device. A preemptive-automatic gain control (AGC) system mitigates a collocated or external interfering signal in a receiver of a portable device. The receiver of the portable device receives and processes a data packet of a first radio frequency (RF) signal that includes a Bluetooth (BT) signal, a Wi-Fi signal, a near field communications (NFC), 3G, 4G, or the like. During the processing of the data packet, a collocated or an external second RF signal is detected and received by the receiver. The second RF signal includes an interfering Bluetooth (BT) uplink transmission, a near field communications (NFC) transmission signal, a Wi-Fi transmission signal, 3G or 4G uplink transmission, an LTE signal, or the like.

Preemptive automatic gain control (AGC) for interference mitigation

Embodiments pertain to systems, methods, and component devices for Tx-Tx transmit concurrency by combining signals before power amplification. One example embodiment includes validity check circuitry configured to check a transmission power for a Bluetooth signal against a first threshold transmission power, a Bluetooth Power Amplifier, and a WLAN power amplifier. A switching network controlled by the validity check circuitry and configured to couple the Bluetooth input to Bluetooth power amplifier input when the transmission power for the Bluetooth signal is above the first threshold transmission power and to couple the Bluetooth signal with a WLAN signal for input to the shared WLAN power amplifier when the transmission power for the Bluetooth signal is less than the first threshold transmission power.

Devices and methods for transmit concurrency by conditioned signal combining

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives an accumulator increment (i.e., the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to an overflow. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input from a pseudo-random noise generator.

Direct digital synthesizer for reference frequency generation

A direct digital frequency synthesizer having a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The multi-modulus divider receives an input clock having an input pulse frequency fand outputs some integer fraction of those pulses at an instantaneous frequency fthat is some integer fraction (1/P) of the input frequency. The multi-modulus divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the numerically controlled oscillator. The numerically controlled oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the multi-modulus divider to change divider ratios in response to receiving an overflow signal. The numerically controlled oscillator also outputs both the overflow signal and a delay signal to the delay generator that further controls the frequency of the multi-modulus divider output signal (V) to provide an output signal (V) with an fthat has improved phase and timing jitter performance over prior art direct digital frequency synthesizer architectures.

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San Carlos, CA, United States of America

Anthony Tsangaropoulos