Rambus Inc.

Clearspeed Technology Limited

Phyworks Limited

Anthony Spencer

Ken Cameron

Gajinder Singh Panesar

Ray McConnell

Paul Winser

Gordon Faulds

Jeff Bond

John Rhoades

Simon McIntosh-Smith

Matthias Dejaegher

Danny Halamish

Nicholas Weiner

Variable size data packets are queued in a communication system by generating from each data packet a record portion of predetermined fixed size containing information about each packet and storing only data portions of the packets in independent memory locations in a first memory. The record portions are only stored in one or more managed queues in a second memory having fixed size memory locations equal in size to the size of the record portions. The first memory is larger than the second memory; and the memory locations in the first memory are arranged in blocks having a plurality of different sizes. The memory locations are allocated to the data portions according to the size of the data portions.

Method and apparatus for queuing variable size data packets in a communication system

A data processing architecture includes an input device that receives an incoming stream of data packets. A plurality of processing elements are operable to process data received from the input device. The input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements.

SIMD array operable to process different respective packet protocols simultaneously while executing a single common instruction stream

An input/output system transfers data packets to and from a SIMD array of processing elements (PEs) such that different sizes of data packets are transferred to respective ones of the PEs. The packets are transferred in batches to respective different addresses in the array under the control of the PEs. Transfer to or from the array may be carried out when either a batch or part of a batch is ready for transfer. The decision to transfer either full or part batches is made in dependence upon the speed of the PEs and the speed and intermittency of the data packets.

Data processing architectures for packet handling using a SIMD array

A state engine receives multiple requests from a parallel processor for a shared state. The state engine includes at least one state element and the at least one state element is adapted to operate, atomically, on the shared state in response to a request made by the parallel processor. The request includes at least a command directing the at least one state element on how to perform an operation on the shared state. The state engine also includes a memory connected to the at least one state element and configured to store the shared state.

State engine for data processor

A data processing architecture comprising:

Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream

Variable size incoming data packets are queued by generating from each data packet a record portion of predetermined fixed size and containing information about the packet. Data portions of the packets are stored in independent memory locations in a first memory while the record portions are stored in one or more managed queues in a second memoryhaving fixed size memory locations matching the size of the record portions. The first memoryis larger than the second memory. The memory locations in the first memory are arranged in blocks having two or more different sizes. Data portions that are too large to be stored in a single memory block are stored as linked lists in a plurality of blocks with pointers pointing to the next block. The memory locations are preferably matched to the most commonly occurring sizes of data packets so that nearly all packets are stored in one respective location. The memory locations in the first memory are preferably allocated from a local poolof available addresses in batches from a central pool

Packet storage system for traffic handling

Data processing architectures

The ordering of packet flows, comprising sequences of data packets, in a communication or computer system, is performed by assigning an exit number to each packet; queuing the packets in a buffer; and outputting the queued packets in a predetermined order according to an order list determined by the exit numbers assigned to each packet before it was queued. The exit number information is preferably assigned to packet records, which are queued in a separate buffer to the packets, the records being of fixed length and shorter than the data portions. The packet record buffer comprises groups of bins, each bin containing a range of exit numbers, the bins for higher exit number packet records having a larger range than bins for lower exit number packet records. Lower exit number packet records in a bin are subdivided into a plurality of bins, each containing packet records corresponding to a smaller range of exit numbers. Secondary bins may be created to temporarily store records assigned to a bin that is currently being emptied. The bins may be filled by a parallel processor, preferably a SIMD array processor.

Data packet handling in computer or communication systems

A switching circuit, for use in soft-decision Extended Hamming Code decoding, allows the detection of pairs of received bits having 'low confidence' and whose position-ids SUM to the syndrome of the received code signal, when the occurrence of an even (and non-zero) number of errors is detected.

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Gloucestershire, United Kingdom

Anthony Spencer