Qualcomm Incorporated

Anthony Segoria

Gurkanwal Singh Sahota

Charles James Persico

Kevin Glenn Gard

Gurkanwal (Kamal) Sahota

Bo Sun

Frederic Bossu

Jorge Garcia

Kevin Gard

An apparatus is disclosed including a tunable passive phase shifter. In example implementations, a phase shifter reuses one or more inductors for multiple bands and can reduce switch use along a propagation path to lower insertion loss. In an example aspect, an apparatus for phase shifting includes a phase shifter having a first port and a second port. The phase shifter includes an inductive path, which is coupled between the first and second ports, and first and second bypass paths. The inductive path includes multiple inductors and multiple nodes. The multiple inductors are coupled together in series between the first and second ports. The multiple nodes are interleaved with the multiple inductors along the inductive path. The first bypass path is coupled to a first pair of nodes of the multiple nodes, and the second bypass path is coupled to a second pair of nodes of the multiple nodes.

Turnable passive phase shifter

Apparatus for generating a first signal (e.g., a pulse) including a current source adapted to generate a current based on a second signal that defines an amplitude of the current and a third signal that defines the timing of an amplitude change of the current, and an impedance element through which the current flows to generate the first signal. The impedance element may comprise a resonator having a resonant frequency approximate the center of the first signal frequency spectrum. An LO may be used to generate the third signal to control the timing of the amplitude change of the current. A detector may enable the current source in response to detecting a defined steady-state condition of the LO clock signal, and may disable the current source in response to the completion of the first signal. A controller may generate the second signal to control the current amplitude so as to perform power control and/or other functions.

System and method for generating a defined pulse

Techniques to reduce LO leakage by controlling the amplitude of LO signal based on the level of output signal after the frequency conversion process. An LO generator receives a VCO signal and generates an LO signal having a variable amplitude and a frequency that is related to the frequency of the VCO signal. A variable gain amplifier receives a control signal and adjusts the amplitude of the LO signal based on the control signal. The variable amplitude LO signal is used for frequency upconversion (e.g., direction upconversion) of an input signal (e.g., at baseband) to obtain an output signal (e.g., at RF). The relationship between LO signal amplitude and output signal level may be defined by a particular transfer function. In general, the LO signal is set higher for higher output signal level and is reduced proportionally for lower output signal level.

Direct conversion with variable amplitude LO signals

An apparatus including cascaded amplification stages adapted to be biased by a common DC current to generate an amplified output signal from an input signal. A first amplification stage includes a routing network to substantially double an input voltage signal, and a first transconductance gain stage to generate a first current signal from the input voltage signal. A second amplification stage includes a resonator to convert the first current signal into a second voltage signal, and a second transconductance gain stage to generate a second current signal from the first current signal. A third amplification stage includes a current gain stage to generate a third current signal from the second current signal, and a load through which the third current signal flows to generate the output signal.

System and method for amplifying a signal using multiple amplification stages sharing a common bias current

Techniques are disclosed for adjusting and programming the duty cycle of a signal generated by a circuit. In an embodiment, parallel transistors are coupled between a NAND gate and a supply voltage. Selectively enabling the parallel transistors adjusts the switching point of the NAND gate, thereby allowing control of the pulse width of the output signal. In an alternative embodiment, the size of the PMOS versus the NMOS transistors in the NAND gate is selectively varied to achieve the same effect. Further disclosed are applications of the techniques to calibrating the receiver to minimize measured second-order inter-modulation products and/or residual sideband.

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San Diego, CA, United States of America

Anthony Segoria