International Business Machines Corporation

Anthony Saporito

Christian Jacobi

Chung-Lung K Shum

James J Bonanno

Timothy John Slegel

Michael K Gschwind

Brian Robert Prasky

Ulrich Mayer

Adam B Collura

Jonathan D Bradbury

Aaron Tsai

Dan F Greiner

Martin Recktenwald

Giles R Frazier

Gregory William Alexander

Markus Kaltenbach

Christian Zoellin

Khary J Alexander

Sheldon Bernard Levenstein

Bruce C Giamei

Jane Helen Bartik

David S Hutton

Donald W Schmidt

Lisa Cranton Heller

Damian Leo Osisek

Marcel Mitran

Robert J Sonnelitter, Iii

Markus Helms

Ashutosh Misra

Eric M Schwarz

Fadi Y Busaba

Alper Buyuktosunoglu

Brian David Barrick

Michael J Cadigan, Jr

Matthias Klein

Cedric Lichtenau

Wolfgang Roesner

Vijayalakshmi Srinivasan

David Allen Hrusecky

Thomas Winters Fox

Brian William Curran

Jonathan T Hsieh

Arun Joseph

John-David Wellman

Hung Qui Le

Charles Franklin Webb

William Vincent Huott

Kailash Gopalakrishnan

Tobias Webel

John Robert Ehrman

Kerstin Claudia Schelm

John G Rell, Jr

Swagath Venkataramani

Jang-Soo Lee

Johannes C Reichart

Daniel Lipetz

Edward Thomas Malley

Michael Billeci

Younes Manton

Volodymyr Paprotski

Bruce Joseph Ronchetti

Daniel V Rosa

Siegmund Schlechter

Simon H Friedmann

Somin Song

James R Mitchell

Simon Weishaupt

Narasimha R Adiga

Jatin Bhartia

David Jon Lee

Douglas G Balazich

Scott Bruce Frommer

Miles Robert Dooley

Stefan Payer

Brenton F Belmar

Sampath Goud Baddam

Christian Borntraeger

Sunil K Shukla

Timothy J Siegel

Willm Hinrichs

James Raymond Cuffney

Randall W Philley

Joran S C Siu

Shashidhar Reddy

Stephen Duffy

John Wesley Ward, Iii

Eyal Naor

Pawel Owczarczyk

Steven J Hnatko

Lawrence Joseph Powell, Jr

Sean Michael Carey

Yair Fried

Joaquin Hinojosa

Ophir Erez

Laith M AlBarakat

Paul Jacob Logsdon

Karl Evan Smock Anderson

Suman Amugothu

Michael Romain

Shimon Ben-Yehuda

A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

System for collaborative hardware RTL logic timing debug in integrated circuit designs

Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

Translation support for a virtual cache

Instruction processing is performed for an instruction. The instruction is configured to perform a function, which is to be performed in a plurality of processing phases. A processing phase is defined to store up to a selected amount of data. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of the function. Based on determining that the store into the designated area occurred, an interrupt is presented.

Program event recording storage alteration processing for a neural network accelerator instruction

A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

Reducing cache transfer overhead in a system

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

Aspects include circuitry that includes a first global generation counter (GGC) that is increased upon decoding of a branch instruction and a second GGC that is increased upon a completion of the branch instruction. Upon a triggered rollback, the first GGC is reset. The circuitry also includes a generation tag memory associated with a register that receives loads during a side-channel attacks which is set to the first GGC upon a first load, and a determination unit to determine, for a second load from an address depending on the register of the first load, a generation tag value associated with the register of the second load as a function of the first GGC, the second GGC, and the generation tag value associated with the register of the first load. A wait queue is configured to block the second load, if the generation tag is larger than the second GGC.

Hardware mitigation for Spectre and meltdown-like attacks

A first processor processes an instruction configured to perform a plurality of functions. The plurality of functions includes one or more functions to operate on one or more tensors. A determination is made of a function of the plurality of functions to be performed. The first processor provides to a second processor information related to the function. The second processor is to perform the function. The first processor and the second processor share memory providing memory coherence.

Neural network processing assist instruction

A method for collaborative logic designing and debugging of a circuit includes initiating, via a session manager, a hardware debug session that includes a plurality of instances of client applications that can access one or more source-codes associated with a logic design of the circuit, the plurality of instances of client applications configured to replicate an execution state of the logic design. The method also includes analyzing, using an instance of a first client application from the plurality of instances of client applications, a defect in the logic design based on the execution state of the logic design. The method also includes editing, using an instance of a second client application from the plurality of instances of client applications, the one or more source-codes, to repair the defect in the logic design.

Heterogeneous services for enabling collaborative logic design and debug in aspect oriented hardware designing

Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

Cache structure using a logical directory

Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes identifying a storage operand request as restrained, where the identifying includes obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction. The access intent indicates usage of the storage operand request is restrained. Further, the method includes determining whether a storage operand request is to a common storage location shared by multiple processing units of a computing environment and is identified restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request.

Temporarily suppressing processing of a restrained storage operand request

A method of performing instruction scheduling during execution in a processor includes receiving, at an execution unit of the processor, an initial assignment of an assigned execution resource among two or more execution resources to execute an operation. An instruction includes two or more operations. Based on determining that the assigned execution resource is not available, the method also includes determining, at the execution unit, whether another execution resource among the two or more execution resources is available to execute the operation. Based on determining that the other execution resource is available, the method further includes executing the operation with the other execution resource.

Instruction scheduling during execution in a processor

Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.

Dynamic selection of OSC hazard avoidance mechanism

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Highland, NY, United States of America

Anthony Saporito