Data General Corporation

Wang Laboratories, Inc.

Anthony S Fong

James Marriot Guyer

Robert D Becker

Martin J Schwartz

Rainer Vogt

Kevin B Normoyle

Janis Delmonte

A data processing system which includes a floating point computation unit (FPU) which interfaces with a central processing unit (CPU) in which the CPU supplies a dispatch control signal to inform the FPU that it is about to execute a floating point macroinstruction and supplies a dispatch address which includes the starting address of the floating point microinstructions therefor during the same operating cycle that the dispatch control signal is supplied. A buffer memory is provided in the FPU to store the starting address of one decoded macroinstruction while a sequence of microinstructions for a previously decoded macroinstruction is being executed by the FPU. When the buffer already has a starting address resident in its buffer the FPU supplies a control signal to prevent the CPU from supplying a further dispatch address until the buffer is empty. Other control signals for synchronizing the CPU and FPU operations and data transfers are also provided.

Floating point unit interface

Apparatus for executing a conditional branch instruction in a pipelined processing unit which has an instruction queue for storing an instruction stream, address generating apparatus connected to the head of the instruction queue for generating and retaining an address defined in the portion of the instruction stream presently at the head of the instruction queue, and instruction interpretation apparatus which is also connected to the head of the instruction queue for receiving and interpreting an instruction at the head of the instruction queue. A conditional branch instruction which is presently at the head of the instruction queue is executed by first performing a dispatch operation in a first cycle which is the last cycle of execution of the instruction preceding the conditional branch instruction in the instruction queue. The dispatch operation sets up the execution of the instruction at the head of the instruction queue. One result of the dispatch operation is the generation of the address for the target instruction specified in the branch instruction. Thereupon, in an immediately following second cycle, a conditional fetch operation and a test operation are performed. The conditional fetch operation provides the address for the target instruction to the processing unit's memory. The test operation determines whether the branch is to be taken. If the branch is not to be taken, the target instruction is not loaded into the instruction queue, the cycle is extended, and a dispatch operation is performed in the extended cycle. If the branch is to be taken, the target instruction is loaded into the head of the instruction queue in the second cycle. Finally, when the branch is taken, the dispatch operation is performed in an immediately following third cycle.

Apparatus and method for executing a conditional branch instruction

An information processing system having a memory for storing instructions and operands, a central processor unit which includes a mechanism for fetching and decoding instructions and operands and a bus connected between the processor unit and memory. An associated floating point unit is coupled to the bus and is responsive to floating point instructions for performing floating point operations. The floating point unit and the central processing unit may perform operations independently of the other or may be synchronized to one another, depending upon the type of instruction. A floating point instruction is determined to be a member of a first group of instructions requiring interlock of operation between the central processor unit and the floating point unit or is determined to be a member of a second group of instructions not requiring interlock of operation. The central processor unit is responsive to the occurrence of an instruction of the first group and to an idle state in the floating point unit for dispatching an instruction of the first group to the floating point unit for execution and is responsive to the occurrence of an instruction of the second group and an available state in the floating point unit for dispatching an instruction of the second group.

Method and apparatus for floating point operations

Improved apparatus for computing locations in compound data items and current lengths in varying-length compound data items when the elements in the compound data items and the varying-length data items have sizes which are powers of 2. The apparatus is used in a digital computer system wherein data items are represented by names associated with name table entry items in memory. The digital computer system's processor includes a name translator for calculating addresses and lengths using the name table entries associated with names. The name table entry associated with a name representing a compound data item or varying-length compound data item having elements whose size is an integer power of 2 includes an element size specifier which has as its value the exponent specifying the power of 2 equal to the size of the elements. When a name table entry for a compound data item includes such an element size specifier, the name translator calculates the displacement of an element in the compound data item or the length of a varying-length data item by shifting an index value specifying one of the elements or a current number of elements value specifying the number of elements currently in the varying-length data item to the left the number of times indicated by the integer value of the element size specifier.

Growing community of inventors

Southboro, MA, United States of America

Anthony S Fong