Intel Corporation

Anthony S Bock

Kevin B Stanton

Ohad Falik

Christopher Hall

Mikal Hunsaker

Frank T Hady

Mason B Cabot

Rick Coulson

Pierre-Louis Bossart

Michael J Greger

Techniques to output a media stream, capture a media stream, or synchronize the output or capture of the media stream at a specified time are described. A media stream output or capture apparatus may include a media processor to receive a media stream to output or a request to capture a media stream and a start time. A buffer generator may be included to generate an input or an output buffer and a media mixer may be included to mix the media stream into the output buffer at the start time or capture the media stream from the input buffer at the start time.

Hardware assisted media playback and capture synchronization

An apparatus for time aware audio streams is described herein. The apparatus includes a converter and an alignment unit. The converter is to perform sample rate conversion of data from a first clock to a second clock. The alignment unit is to indicate valid sample points in the data based on a relationship between the first clock and the second clock.

Time aware audio streams with heterogenous frame rates

In accordance with embodiments disclosed herein, there is provided systems and methods for time offset validation of components with independent silicon clocks. A requesting component includes transmission logic to transmit timing protocol requests to a responding component, receiving logic to receive timing protocol responses, replay detection logic to detect a retransmission of a timing protocol message and to set an internal timing state of the requesting component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the requesting component as valid. A responding component includes receiving logic, transmission logic, replay detection logic to detect a retransmission of a timing protocol message and set an internal timing state of the responding component as invalid, and validation logic to detect at least two consecutive timing protocol dialogs and set the internal timing state of the responding component as valid.

Time offset validation of components with independent silicon clocks

Methods and apparatus relating to measuring time offsets between devices with independent silicon clocks are described. In some embodiments, logic is provided to synchronize a first clock of a first agent with a second clock of a second agent based on one or more messages exchanged between the first agent and the second agent and a platform time. The first agent and the second agent are coupled via a link. Other embodiments are also disclosed and claimed.

Measuring time offsets between devices with independent silicon clocks

A method and system are disclosed for measuring simultaneously and at randomly distributed intervals throughputs sets on one or more busses under test and displaying the percent occurrences of those throughputs sets in a graph as a density function. A method and system are also disclosed for simultaneously measuring throughput sets on one or more busses under test given that user specified stimuli are input into those busses and displaying those throughput sets in a graph as concurrency plots.

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Vancouver, WA, United States of America

Anthony S Bock