International Business Machines Corporation

Anthony P Ingraham

Voya Rista Markovich

Jaynal Abedin Molla

Gary Ray Hill

Mark Vincent Pierson

Michael D Lowell

Sanjeev Balwant Sathe

Glenn L Kehley

Kibby B Horsford

Gordon C Osborne, Jr

John R Slack

Richard Gordon Charlton

Mark Andrew Couture

George Frederick Walker

James Robert Wilcox

Jerome A Frankeny

Thomas P Gall

Francis Joseph Downes, Jr

James Steven Kamperman

George Charles Correia

Paul Alfred Lauro

David John Russell

Jerome J Cuomo

Sung Kwon Kang

David Noel Light

Douglas Oliver Powell

Christina Marie Boyko

John J Ritsko

Stephen Joseph Fuerniss

Perminder S Bindra

Jungihl Kim

George J Saxenmeyer, Jr

Jack A Varcoe

Ekkehard F Miersch

Richard Gerald Murphy

David Brian Stone

Anilkumar Chinuprasad Bhatt

Bahgat Ghaleb Sammakia

William T Chen

Morris Anschel

Robert Douglas Edwards

Richard Stuart Zarr

Scott D Reynolds

Timothy Shawn Reny

Paul Joseph Hart

Charles Robert Lamb

Wayne R Storr

Wolfgang Mayr

Tamar A Powers

George C Correla

Leo Raymond Buda

George John Saxenmeyer, Jr

Bette Jaye Whalen

A method of testing semiconductor chips is disclosed. The individual semiconductor chips have I/O, power, and ground contacts. In the method of the invention a chip carrier is provided. The chip carrier has contacts corresponding to the contacts on the semiconductor chip. The carrier contacts have dendritic surfaces. The chip contacts are brought into conductive contact with the conductor pads on the chip carrier. Test signal input vectors are applied to the inputs of the semiconductor chip, and output signal vectors are recovered from the semiconductor chip. After testing, the chip may be removed from the substrate. Alternatively, the chip may be bonded through the dendritic conductor pads to the substrate after successful testing.

Method and apparatus for in-situ testing of integrated circuit chips

An efficient cooling mechanism for a multi-chip carrier can be provided while conserving board surface area. Flexible circuitized material is used to form multi-chip carriers with air baffle capability. The flex is folded or curved into the desired shape and held in position with a support structure. Bonding sites for chips are located on regions through the carrier. Shapes which provide air baffle capabilities include coils, spring-like coils and serpentines.

Free standing, three dimensional, multi-chip, carrier package with air flow baffle

According to the present invention a technique for providing a planarized substrate with dendritic connections of solder balls, especially a multi-layer ceramic substrate is provided. In the case where the substrate has a raised central portion on the top surface on which are disposed top surface metallurgy pads, a layer of conformable photoimagable material is placed over the top surface. The photoimagable material is exposed and developed in a pattern corresponding to the pattern of the top surface metallurgy pads to form vias in the photoimagable material. Copper is plated in the vias in contact with the top surface metallurgy pads. The exposed surface of the photoimagable surface is then planarized, preferably by mechanical polishing to form a flat planar surface, with the ends of the vias exposed. Dendritic connector pads are then grown on the exposed ends of the vias to which solder ball connections of an I/C chip are releasably connected.

Method of planarizing a curved substrate and resulting structure

A solder interconnection uses preferably lead-rich balls for making a low temperature chip attachment directly to any of the higher levels of packaging substrate. After a solder ball has been formed using standard processes, a ball limiting metal mask is formed using photoresist. A thin cap layer of preferably pure tin is deposited on a surface of the solder balls using a tin aqueous immersion process.

Interconnect structure for joining a chip to a circuit card

A technique for testing/stressing integrated circuit devices, especially wafers, having a plurality of contacts on one face thereof arranged in a predetermined pattern is provided. An interposer having a dielectric substrate and a device contact face and a tester contact face is provided. A first plurality of releasable connectors on the device contact are face arranged in the same predetermined pattern, and a second plurality of releasable connectors are arranged in the same predetermined pattern on the tester contact face. The releasable connections are formed of dendrites. Conducting vias connect the corresponding connectors of the first and second releasable connectors respectively. A test head is provided having a plurality of contact pads also arranged in the same predetermined pattern. Circuitry is provided on the test head to connect each of the contact pads thereon with external leads extending to provide signal contact to each of the contact pads on the test head. The interposer is positioned between the IC device and the test head, with the contacts on the IC device in contact with the first plurality of connectors and the contact pads on the test head in contact with the second plurality of connectors. Signals are provided to the connector pads from the electrical leads for performing testing and/or burn-in of the integrated circuit device. The testing is performed at elevational temperatures. A test head structure is also disclosed.

Apparatus and method for burn-in/testing of integrated circuit devices

Test head for applying signals in a burn-in test of an integrated circuit

Electrically conductive lamina are attached by an electrically insulating, thermally conductive adhesive and/or solder to one or more semiconductor devices such as chips and extend beyond the periphery of the chip or chips to form heat sink fins. Electrical connections may be made between such chips through holes (e.g. by a wire or plated through hole) in the electrically conductive lamina lined with an insulating material such as the electrically insulating adhesive to provide a structurally robust assembly. Surface pads and connections may overlie patterns of insulator on the lamina. A further lamina can be wrapped around lateral sides of the assembly to provide further heat sink area and mechanical protection for other heat sink fins. A graphite/carbon fiber composite matrix material is preferred for the lamina and the coefficient of thermal expansion of such materials may be matched to that of the semiconductor material attached thereto. Conductivity of the lamina also provides shielding against electrical noise to improve the noise immunity of short connections between chips made through the lamina as well as that of surface connections which may be formed on the lamina.

Integrated, multi-chip, thermally conductive packaging device and

Free standing, three dimensional, multi-chip, carrier package with air

An apparatus, and a corresponding method, for stress-testing wire bond-type semiconductor chips is disclosed. The apparatus includes a clamp housing, with a spring-loaded screw extending through the top end of the housing. Contained within the clamp housing is a substantially rigid, electrically insulating base plate positioned at a lower end of the clamp housing. The upper surface of the base plate includes a depression which contains an insert fabricated either from an elastomeric material or a semiconductor material, such as silicon. A flexible, electrically insulating layer made from, for example, polyimide, overlies the base plate and insert. Significantly, the upper surface of the flexible, electrically insulating layer includes a plurality of dendritic contacts. It is through these dendritic contacts that electrical contact is made to the contact pads of a wire bond-type semiconductor chip.

Apparatus, and corresponding method, for stress testing wire bond-type

Ball limiting metal mask and tin enrichment of high melting point solder

A multi-chip carrier which uses less lateral mounting space on the surface of a circuit board or card can be formed using flexible circuitized material. Lateral space is compressed by utilizing more vertical space to package chips and components. The problem of cooling multiple chips in a tight space may be accomplished by integrating the heat sink in with the circuit carrier and having the heat sink double as a support structure. A flex material is folded or shaped. Different regions of the flex are used for mounting chips, mounting support mechanisms, or mounting the structure on a carrier or substrate.

Vertically integrated multi-chip circuit package with heat-sink support

A technique of connecting a first member having a first face to a second member having a second face utilizing dendrites is provided. Dendrites are formed on one face of the first member in a given configuration. Dendrite receiving and securing material, preferably solder, is formed on a face of the second member in a configuration confirming substantially to the given configuration of the dendrites on the one face. The first and second members are then placed in a position relative to each other with the dendrites on the one face of the first member in contact with the dendrite receiving and engaging material on the face of the second member. An airtight seal is then provided between the first and second faces surrounding the dendrites and dendrite receiving and engaging material, which forms a sealed chamber between the first and second members. Thereafter, a vacuum is pulled within the sealed chamber, thereby causing the ambient air pressure on the two members to urge the two members toward each other which will embed the dendrites in the dendrite receiving and engaging material to form interconnection therebetween. In order to enhance or improve the bond between the dendrites and the dendrite receiving and securing material, the dendrites and dendrite receiving and securing material each contain a component which can form an intermetallic compound therebetween.

Dendritic interconnection system

A dendrite surface is provided on each of the electrical contacts of a substrate, such as a test board, chip carrier, or printed wiring board. The electrical contacts on the substrate are arranged in a mirror image of the input/output pads on a wirebond chip from which the wire leads have been removed from, or not initially provided on, each of the input/output pads. The wirebond chip is aligned with the substrate, and the respective contact brought into electrical communication with each other. The wirebond chip may be removed after testing or other temporary attachment purpose, or permanently encapsulated with at least a portion of the substrate in a permanent assembly. The present invention permits wirebond chips to be selectively attached temporarily or permanently, i.e., have a pluggable capability, as well as the ability to allow a full array of I/O pad design.

Method of forming a solderless electrical connection with a wirebond chip

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Endicott, NY, United States of America

Anthony P Ingraham