Apple Inc.

Advanced Micro Devices Corporation

Anthony P DeLaurier

Tyson J Bergland

Karthik Ramani

Winnie W Yeung

Michael J Swift

Abdulkadir U Diril

Kenneth Christian Dyke

Gokhan Avkarogullari

Srinivasa Rangan Sridharan

David A Gotwalt

Karl D Mann

Muditha Kanchana

Wolfgang H Klingauf

Michal Valient

Stephan Lachowsky

Luc R Semeria

Adam T Moerschell

Robert S Hartog

Michael Mantor

Terence M Potter

Aaftab A Munshi

Mark Fowler

Mark M Leather

Christopher A Burns

Robert Scott Hartog

Andrew S Pomianowski

Brian A Buchner

Owen C Anderson

Marcos Zini

Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, amounts of data needed to represent, using a given lossless compression technique of the multiple lossless compression techniques, individual pixels in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on comparison, among the compression techniques, of sums of: the determined amount of data for an individual pixel for a given lossless compression technique and compression metadata size for a given lossless compression technique. The compression circuitry may generate and store information that encodes values for the set of pixels using the selected compression technique.

Lossless compression techniques

Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, a memory system implements a storage hierarchy that includes first cache circuitry and second cache circuitry at different levels of the hierarchy. Processor circuitry generates write data to be written to the memory system. In some embodiments, first compression circuitry is configured to compress a first block of write data in response to full accumulation of the first block in the first cache circuitry and second compression circuitry is configured to compress a second block of write data in response to full accumulation of the second block in the second cache circuitry. Write circuitry may write the first and second compressed blocks of data in a single combined write to a higher level in the storage hierarchy.

Compression techniques and hierarchical caching

Techniques are disclosed relating to data compression. In some embodiments, compression circuitry determines, at least partially in parallel for multiple different lossless compression techniques, a number of bits needed to represent a least compressible pixel, using that technique, in a set of pixels being compressed. The compression techniques may include neighbor, origin, and gradient techniques, for example. The compression circuitry may select one of the compression techniques based on the determined numbers of bits for the multiple compression techniques and corresponding header sizes. In some embodiments, the compression circuitry determines, for multiple regions of pixels in the set of pixels, for ones of the compression techniques, a region number of bits needed to represent a least compressible pixel, using that technique. The selection of a compression technique may be further based on region numbers of bits.

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

Graphics surface addressing

Techniques are disclosed relating to compression of data stored at different cache levels. In some embodiments, programmable shader circuitry is configured to execute program instructions of compute kernels that write pixel data. In some embodiments, a first cache is configured to store pixel write data from the programmable shader circuitry and first compression circuitry is configured to compress a first block of pixel write data in response to full accumulation of the first block in the first cache circuitry. In some embodiments, second cache circuitry is configured to store pixel write data from the programmable shader circuitry at a higher level in a storage hierarchy than the first cache circuitry and second compression circuitry is configured to compress a second block of pixel write data in response to full accumulation of the second block in the second cache circuitry. In some embodiments, write circuitry is configured to write the first and second compressed blocks of pixel data in a combined write to a higher level in the storage hierarchy.

Compression techniques for pixel write data

Systems, apparatuses, and methods for efficiently allocating data in a cache are described. In various embodiments, a processor decodes an indication in a software application identifying a temporal data set. The data set is flagged with a data set identifier (DSID) indicating temporal data to drop after consumption. When the data set is allocated in a cache, the data set is stored with a non-replaceable attribute to prevent a cache replacement policy from evicting the data set before it is dropped. A drop command with an indication of the DSID of the data set is later issued after the data set is read (consumed). A copy of the data set is not written back to the lower-level memory although the data set is removed from the cache. An interrupt is generated to notify firmware or other software of the completion of the drop command.

Cache drop feature to increase memory bandwidth and save power

Techniques are disclosed relating to memory allocation for graphics surfaces. In some embodiments, graphics processing circuitry is configured to access a graphics surface based on an address in a surface space assigned to the graphics surface. In some embodiments, first translation circuitry is configured to access one or more entries in a set of multiple translation entries for pages of the surface space (where the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space) and translate address information for the surface space to address information in the virtual space based on one or more of the translation entries. In some embodiments, the graphics processing circuitry is configured to provide an address for the access to the graphics surface based on translation by the first translation circuitry and second translation circuitry configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The disclosed techniques may allow sparse allocation of large graphics surfaces, in various embodiments.

Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.

Level of detail offset determination

Techniques are disclosed relating to memory consistency in a memory hierarchy with relaxed ordering. In some embodiments, an apparatus includes a first level cache that is shared by a plurality of shader processing elements and a second level cache that is shared by the shader processing elements and at least a texture processing unit. In some embodiments, the apparatus is configured to execute operations specified by graphics instructions that include (1) an attribute of the operation that specifies a type of memory consistency to be imposed for the operation and (2) scope information for the attribute that specifies whether the memory consistency specified by the attribute should be enforced at the first level cache or the second level cache. In some embodiments, the apparatus is configured to determine whether to sequence memory accesses at the first level cache and the second level cache based on the attribute and the scope.

Memory consistency in graphics memory hierarchy with relaxed ordering

Techniques relating to serial processing of pixels in a texture processing pipeline. In some embodiments, the pipeline receives pixel data for a set of pixels in parallel but processes the pixels in the set serially in a pipelined fashion. In some embodiments, the pipeline includes a stage configured to retain texel data for use by a subsequently processed pixel. They may allow overlapping texels to be fetched once for the set of pixels rather than multiple times for different pixels in the set. In some embodiments, the pipeline uses a selected ordering of serial processing for the pixels, where the ordering increases the potential for texel overlap, relative to one or more other orderings.

Serial pixel processing with storage for overlapping texel data

Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.

Storage element with multiple clock circuits

Techniques are disclosed relating to interpolation for texture mapping. In some embodiments, a graphics unit includes circuitry configured to map a texture to a screen space such that a set of multiple in the screen space falls between first and second adjacent texels of the texture in a first dimension. In some embodiments, the graphics unit also includes texture processing circuitry configured to perform different types of interpolation for pixels in the group of pixels. In these embodiments, this includes determining pixel attributes for first and second end groups of pixels in the set of pixels using a nearest-neighbor interpolation technique and attributes of the first and second texels respectively. In these embodiments, this also includes determining pixel attributes for an intermediate group of pixels in the set of pixels using a second, different interpolation technique and attributes of both the first and second texels.

Interpolation circuitry and techniques for graphics processing

Apparatus and systems utilizing fixed point filtering to perform floating point texture filtering. A texture pipe unit consisting of a texture addressing unit, texture cache unit, and texture filter unit accepts texture requests for a specified pixel from a resource and returns formatted bilinear filtered results based on the specific pixel's corresponding four texels. The texture filtering unit consists of a pre-formatter module, interpolator module, accumulator module and a format module. The pre-formatter module accepts texel data in a floating point or fixed point format. However, if the data is in a floating point format the pre-formatter module converts the floating point data into a normalized fixed point data format whereby the interpolator module may perform its bilinear interpolator functions using standardized fixed point systems and apparatus without necessitating the use of floating point arithmetic units. A method utilizing fixed point filtering to perform floating point texture filtering is also presented.

Floating point texture filtering using unsigned linear interpolators and block normalizations

A shader pipe texture filter utilizes a level one cache system as a primary method of storage but with the ability to have the level one cache system read and write to a level two cache system when necessary. The level one cache system communicates with the level two cache system via a wide channel memory bus. In addition, the level one cache system can be configured to support dual shader pipe texture filters while maintaining access to the level two cache system. A method utilizing a level one cache system as a primary method of storage with the ability to have the level one cache system read and write a level two cache system when necessary is also presented. In addition, level one cache systems can allocate a defined area of memory to be sharable amongst other resources.

Growing community of inventors

Los Altos, CA, United States of America

Anthony P DeLaurier