Arm Limited

Anthony Neil Berent

Andrew Brookfield Swaine

David James Williamson

Ian Victor Devereux

Robert James Catherall

Jonathan William Brawn

Paul Robert Gotch

Rhys David Copeland

Jonathan Stephen Black

Paul Frederick D'Souza

Conrado Blasco Allué

Mark Edgeworth

Simulation of execution of a processing workload by a target hardware device is provided by providing workload data specifying the processing workload, passing the workload data to both a primary partial simulation and a complementary partial simulation that run in parallel and acquire input data from different levels of abstraction of the target hardware and then simulating execution of the processing workload using a primary partial simulation to generate primary partial result state data and using the complementary partial simulation to generate complementary partial result state data. The target hardware device may be a graphics processing unit and the workload data may specify the processing to be performed in a hardware independent form, such as, for example, OpenGL ES. The host system supporting the simulation may include a graphics processing unit serving to provide the complementary partial simulation due to its own execution of the workload data.

Hardware simulation

An encoding method generates an encoded image according to a predetermined encoding format. The method includes the step of, for each block of pixels, determining an average color of colors of the block of pixels in the predetermined color space; selecting at least one luminance line in dependence on an offset in the color space of the average color from the at least one luminance line; identifying a set of candidate base colors lying on the at least one luminance line; and determining, using the set of candidate base colors and the luminance offset values, the set of encoded pixel colors. The base color and the set of luminance offsets are selected in dependence on an encoding error indicative of a sum distance in the color space between the set of encoded pixel colors and the colors of the block of pixels.

Image encoding using base colors on luminance line

The present invention provides a system and method for controlling a simulator to run a software simulation of a data processing system in order to generate simulated timing data indicative of performance of an unmodelled portion of the data processing system not modelled by the software simulation. The software simulation provides a timing accurate model of those parts of the data processing system other than the unmodelled portion. The method of the invention comprises inputting to a controller of the simulator real trace data obtained from execution of a program by the data processing system, the real trace data identifying the sequence of instructions executed by the data processing system, and associated timing data. The method then involves running the software simulation under the control of the controller, the controller determining from the real trace data the sequence of instructions executed by the data processing system and controlling the software simulation to ensure that the same sequence of instructions is executed within the software simulation. Then simulated timing data is generated resulting from execution of the sequence of instructions within the software simulation, whereby the performance of the unmodelled portion of the data processing system is derivable from a comparison of the real trace data and the simulated timing data. This technique provides a particularly efficient technique for obtaining performance information about a portion of a data processing system which is not modelled within a software simulation.

Analysis of the performance of a portion of a data processing system

The present invention relates to a data processing apparatus and method for compiling application code. The data processing apparatus comprises a processor, and a compiler for compiling application code to generate instructions for execution by the processor. Furthermore, a non-invasive trace unit is coupled to the processor for generating, from input signals received from the processor, trace signals indicative of the instructions being executed by the processor. The compiler is then arranged to control the compilation of the application code dependent on the trace signals. The non-invasive nature of the trace unit enables it to generate trace signals that can be used to produce profiling information for use by the compiler without altering the behaviour of the code being executed by the processor, and accordingly provides a significantly improved technique for obtaining profiling information for use in feedback driven optimization compilation techniques.

Compilation of application code in a data processing apparatus

The present invention provides an apparatus and method for facilitating debugging of sequences of processing instructions. The apparatus comprises a processing circuit for executing processing instructions, the processing circuit having multiple states of operation, with each state of operation being assigned a context identifier to identify the state of operation. Further, logic is provided for facilitating debugging of sequences of processing instructions executed by the processing circuit. The logic comprises control logic, responsive to control parameters, to perform predetermined actions to facilitate debugging, and triggering logic for generating the control parameters dependent on data received from the processing circuit indicative of the processing being performed by the processing circuit. The triggering logic comprises at least one context identifier comparator for comparing a context identifier provided within the data received from the processing circuit with a predetermined context identifier, and to generate a signal indicating whether that context identifier matches the predetermined context identifier. By this approach, the present invention enables a data processing apparatus to be provided with tracing mechanisms and/or debugging mechanisms which can reliably operate even in situations where the sequences of processing instructions from different states of operation occupy overlapping regions in the memory's address space.

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Cambridge, United Kingdom

Anthony Neil Berent