Texas Instruments Corporation

Anthony Martin Hill

Jose Luis Flores

Francisco A Cano

Uming U Ko

Devanathan Varadarajan

Nagaraj Narasimh Savithri

Haydar Bilhan

John Chrysostom Apostol

Jian-Yi Wu

Usha Narasimha

Yongjie Jiang

Richard D Simpson

Donald Edward Steiss

Alan David Hales

Richard P Wiley

Mayur Joshi

An adaptive voltage scaling technique includes using a temperature sensor arranged on a semiconductor die to determine a current die temperature of the semiconductor die, using a performance sensor arranged on a semiconductor die to determine a current performance metric of the semiconductor die, determining whether the current performance metric matches an expected performance metric based at least partially on the current die temperature and, if the current performance metric does not match the expected performance metric, indicate a performance sensor error, when a performance sensor error is indicated, determining an updated power supply voltage for correcting the performance sensor error, and causing a current power supply voltage supplied by a power supply voltage source of the semiconductor die to be changed to the updated power supply voltage.

Adaptive voltage scaling using temperature and performance sensors

Systems of screening memory cells of a memory include modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven with respect to a nominal operating voltage on the wordline. In a write operation, one or both of the bitline and wordline may be overdriven or underdriven with respect to corresponding a nominal operating voltage. Such a system has margin control circuity, which may be in the form of bitline and wordline margin controls, to modulate bitline and wordline voltages, respectively, in the memory cells of the memory array.

Screening of memory circuits

Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.

Methods and apparatus for providing a time-interleaved current-feedback droop function for multiphase buck converters. An example method includes outputting a first control signal to enable a first set of switches corresponding to a first voltage of a first phase from a multiphase converter, the first phase included in a plurality of phases; enabling a first current associated with the first phase to be measured by a sample and hold circuit associated with the first phase; sampling the first current; holding the first current, the first current based on a load current for the first phase of the multiphase converter; and outputting a droop voltage based on a plurality of currents corresponding to the plurality of phases of the multiphase converter, the plurality of currents including the load current for the first phase.

Time-interleaved current feedback droop function for multiphase buck converters

The invention is an intelligent connection of the internal scan logic in a multi-bit flip-flop register. Individual bits in this register are connected in a serial scan chain. In this invention the serial chain is connection reuses logic between slave latches on bit n and master latches on bit n+1. This reuse reduces the number of transistors required to implement the multi-bit register. This reduction in the number of required transistors enables a consequent reduction in integrated circuit area required, thereby reducing manufacturing cost. Alternatively, the area saved using this invention may be used for other purposes. This could increase the value of the corresponding integrated circuit without increasing manufacturing costs.

Area efficient multi bit flip flop topologies

This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.

Accurate integrated circuit performance prediction using on-board sensors

An integrated circuit is provided with a set of sensors for scaling voltage based on performance of the integrated circuit. The set of sensors are monitored, and sensor provides an output value indicative of a performance metric of the integrated circuit. The output values from the set of sensors are combined using a calibrated model to determine when a threshold value is reached. A change to an operating voltage for a portion of the integrated circuit is initiated in response to reaching the threshold.

Closed loop adaptive voltage scaling

A novel approach to cross-talk analysis takes effective account of the nature of cross-talk interference. This approach employs conservative assumptions regarding (1) the equivalent output resistance, and (2) the definition of noise immunity for the victim gate. Also, this approach uses signal and noise current metrics in modeling the parameters of the active device elements. This approach provides an expectation of detection and elimination of noise hazards that might otherwise not be undetected.

Accurate noise modeling in digital designs

The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.

Method for circuit sensitivity driven parasitic extraction

An integrated circuit includes an external reset input, a clock input for receiving a clock signal and a reset signal sub-circuit including an internal reset output connected to other circuits of the integrated circuit. The reset signal sub-circuit immediately supplies an internal reset signal upon receipt of the external reset signal and ceases to supply the internal reset signal upon a next clock signal following ceasing to receive the external reset signal. This asynchronously forces combinational logic to a reset state upon receipt of the internal reset signal and synchronously forces sequential logic to a reset state upon receipt of a next clock signal.

On-chip reset circuitry and method

In a scannable D master-slave flip-flop circuit with synchronous preset or clear capability, the output of the slave latch is gated with the scan-enable signal to form the scan-data-output signal. This output gating of the scan-output data that allows for considerable simplification of the input logic. This simplification also provides for the reduction in both the size and the number of transistors in the input logic. This in turn is multiplied many tens of thousands of times in a complex processor chip, resulting in a substantial reduction in chip power and silicon area usage.

Power reduction in scannable D-flip-flop with synchronous preset or clear

In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A multi-dimensional noise lookup table is formed for a cell used within the IC, wherein the multi-dimensional noise table relates a set of input noise pulse characteristics and a set of output loading characteristics to an output noise pulse characteristic of the cell. A noise pulse on an input to an instantiation of a cell is determined and then characterized. An output loading characteristic of the cell is also made. A prediction of whether the instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic. Other instantiations of the cell are evaluated using the same multi-dimensional noise table. A prediction of whether each instantiation of cell will propagate the noise pulse is made by selecting an output noise pulse characteristic from the multi-dimensional noise table corresponding to the noise pulse characteristic and to the output loading characteristic associated with each instantiation of the cell.

Cell-based noise characterization and evaluation

A combination NAND and flip-flop circuit includes a pre-NAND scan circuit operable to receive a plurality of input signals and produce first and second output signals for receipt by a NAND gate. The plurality of signals comprises signals indicative of a first data signal, a second data signal, a scan-in signal, and a scan-enable signal. These circuits include a NAND gate having first and second inputs operable to receive the first and second output signals of the pre-NAND scan circuit. They also include a first transmission gate and a first inverter. The transmission gate receives the output of the NAND gate and the inverter receives the output of the transmission gate. The pre-NAND scan circuit is operable to produce the first and second output signals based on the plurality of input signals such that the first and second output signals are defined as described below. When the scan-enable signal is equal to a logical one then the first output signal and the second output signal are either both equal to the scan-in signal or the first output signal is equal to a logical one and the second output signal is equal to the scan-in signal. When the scan-enable signal is equal to a logical zero, then the first output signal is equal to the first data signal and the second output signal is equal to the second data signal.

Integrated NAND and flip-flop circuit

A computer system ( ). The computer system comprises processing circuitry ( ) and storage circuitry ( ) for storing a plurality of files. The plurality of files include a circuit description file ( ) comprising data describing devices and signals in a circuit. The plurality of files also include a plurality of list expressions ( ) relating to one of devices, signals, or devices and signals described by the data in the circuit description. Still further, the plurality of files also include a plurality of rules ( ). The processing circuitry is programmed to perform various steps. These steps include processing ( ) the plurality of list expressions to extract a plurality of lists in response to the circuit description. Each of the plurality of lists comprises a non-negative integer number of elements. The programmed steps further include processing ( ) the plurality of rules to evaluate one or more of the plurality of lists to verify connection accuracy within the circuit in response to the non-negative integer number of elements.

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Dallas, TX, United States of America

Anthony Martin Hill