Motorola Corporation

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Continental Teves, Ag and Company Ohg

Anthony M Reipold

Kenneth L McIntyre, Jr

Daniel W Pechonis

Manfred P Thanner

Gary R Morrison

Jose A Lyon

Stephan G Mueller

William C Moyer

Florian Bogenberger

Brian Christopher Kahne

Adrian Traskov

Kirk Samuel Livingston

Oleksandr Sakada

Alexandre Pierre Palus

Andreas Kirschbaum

Lukusa Didier Kabulepa

Steven P Lindquist

Nancy H Amedeo

Colleen M Collins

Tony Tong-Khay Cheng

Houman Amjadi

Eric Hoang

Robert L Winter

In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Multi-channel network-on-a-chip

An integrated circuit device comprising at least one memory interface module arranged to be operably coupled between at least one data storage device and a plurality of master devices within a data processing system. The at least one memory interface module comprises a plurality of buffers and at least one data access control module. The at least one data access control module being arranged to fetch data from the at least one data storage device in response to a received memory access request comprising a master device identifier, select at least one buffer based at least partly on the master device identifier of the received access request, and load the fetched data into the selected at least one buffer.

Integrated circuit device and method for providing data access control

An approach is provided in which a set of common instructions are each executed by at least two processor cores. Each of the processor cores queues values resulting from at least one of the common instructions (a critical section). The queued values are compared by a queued comparator. An exception is issued in response to the comparison revealing unequal values having been queued by the processor cores.

Compiler optimized safety mechanism

A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.

Synchronization of stateful elements in a processing resource using a scan chain

A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product

A method for testing at least one logic block of a processor includes, during execution of a user application by the processor, the processor generating a stop and test indicator. In response to the generation of the stop and test indicator, stopping the execution of the user application and, if necessary, saving a state of the at least one logic block of the processor. The method further includes applying a test stimulus for testing the at least one logic block of the processor. The test stimulus may be shifted into scan chains so as to perform scan testing of the processor during normal operation, such as during execution of a user application.

Method and apparatus for testing a data processing system

A data processing system (10) capable of burst transfers having an external bus interface (30) which allows termination of a burst transfer prior to completion of the burst transaction. The present invention offers a method of terminating a burst transaction without the addition of wait states, and further allows termination to effectively interrupt the burst transaction rather than waiting for burst completion. In one embodiment, on the negation of a burst request signal during a burst transfer, external bus interface (30) terminates the burst transfer without waiting for the completion of the burst transaction.

Method and apparatus for burst protocol in a data processing system

A data processing system (20) having a burst address generator (BAG) 55, with a programmable transaction mode applicable to both cache and pre-fetch architecture types. BAG 55 asserts a data acknowledge (DTACK) signal to end a burst transfer on either a physical boundary, as in pre-fetch mode at the end of a row in a memory device, or a limit detection, as in cache mode where the limit is determined by the length of a cache line. BAG 55 increments the burst address internally, and for operations in pre-fetch mode, the user determines if the incremented address is provided external to data processor (22).

Method and apparatus for adaptable burst chip select in a data

A data processing system (20) having programmable chip select signal negation. A user programmable 'NEGATE EARLY' value generates a chip select negation one bus cycle before the end of a transaction, giving an external device additional time to disconnect from the current bus cycle before the start of the next bus cycle. Early negation of a chip select signal provides an efficient method of interface with slower devices while providing adding functionality to the chip select signal.

Method and apparatus for programmable chip select negation in a data

A data processing system (20) having a high performance chip select (HPCE) signal, which is functionally programmable to remain asserted for a predetermined number of bus cycles based on an access duty cycle. Bits in an option register (52) allow the user to program HPCE for maintained assertion always, never, or for a number of cycles after a last valid address match. Continued assertion reduces access time to an external device allowing the user to determine the trade-off between high speed access and low power consumption. Additionally, a speculative burst access is made without regard to match criteria, allowing a device to prepare for access while data processor (22) determines the next device to access. Here a load burst address (LBA) signal is speculatively provided to an activated device, and where the next access is to another device, the speculative access is aborted.

Method for accessing memory by activating a programmable chip select

A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

Growing community of inventors

Austin, TX, United States of America

Anthony M Reipold