Intrinsity, Inc.

Evsx, Inc.

Advanced Micro Devices Corporation

Apple Inc.

Anthony M Petro

James S Blomgren

Terence M Potter

Stephen C Horne

Michael R Seningen

Brian D McMinn

The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Method and apparatus for a 1 of N signal

A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Method and apparatus for a N-NARY logic circuit using capacitance isolation

The present invention is an incrementor that receives as inputs a 32-dit 1-of-4 operand and a 1-of-2 increment control signal. For each dit of the operand, the present invention determines whether the increment control signal, which is treated as a carry into the least significant dit, propagates into said dit. If so, the value of the dit is incremented. Otherwise, the dit value is output without modification. The present invention also generates a carry out signal if the increment control signal has propagated across all dits.

Method and apparatus for N-nary incrementor

The present invention comprises a method and apparatus that selectably performs either addition or subtraction on two N-nary operands to generate an intermediate, then final, N-nary final result. If the intermediate result of the operation contains less bits than a full register, the intermediate result is &ldquo;merged&rdquo; with the second operand in that unaltered bits from the second operand are bypassed to the final result. Accordingly, the final result and the second operand have an equal number of bits.

Dynamic 3-level partial result merge adder

The present invention includes a partial register write handler. The write handler receives either two or three operands. An execution unit operates on portions of two operands, rather than on full operands. The result of the execution unit has fewer bits than an &ldquo;additional&rdquo; operand, which may be any of the two or three operands received by the write handler. An output multiplexer receives all of the bits of an execution unit result and selected bits of the additional operand, and produces an output that has as many bits as the additional operand. If the output of the multiplexer is a string of bits, the string of bits contains the execution unit result as a substring of bits. The remaining bits of the output of the multiplexer are selected from the additional operand.

Method and apparatus for handling partial register accesses

The present invention comprises a multi-function shifter that uses N-nary logic and includes an operation selection and various 1-of-N multiplexers to support a variety of shift modes. The shift modes include rotates, logical shifts in which 0 is shifted into any vacated bit positions, and arithmetic shifts in which the value of the original most significant bit is shifted into any vacated bit positions. The present invention includes a general 32-bit shifter that can shift an arbitrary number of places in a single cycle, using any of the modes described above.

Method and apparatus for a 1 of 4 shifter

An apparatus that performs arithmetic logic and carry-lookahead logic in parallel on two N-nary operands, including saturating or unsaturating, signed or unsigned, addition or subtraction. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries. Each selectable feature may be implemented singly, or in combination with other selectable features.

Method and apparatus for dynamic partitionable saturating adder/subtractor

An apparatus and method for performing saturating addition or subtraction on two signed or unsigned operands using N-NARY logic. The two operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. For multiple partitions, carry propagation is interrupted on partition boundaries so that partitions may be saturated independently.

Method and apparatus for saturation in an N-NARY adder/subtractor

The present invention comprises a master global clock distributed in a low-skew manner over a relevant clock domain area coupled with a plurality of locally generated clocks in said clock domain area. The plurality of locally generated clocks are tuned to allow for skew and jitter tolerance. The present invention further comprises embodiments with 3, 4, 5, and 6 locally generated clocks.

Method and apparatus for generating clock signals

The described multiplier provides the signed or unsigned product of a multiplicand and multiplier represented in preferably 1-of-4 N-NARY signals by performing a preferably radix-four Booth recoding of the multiplier, producing partial products using a plurality of Booth multiplexers, summing the partial productsto produce two intermediate partial products using a six-level Wallace tree, and summing the two intermediate partial products using a carry lookahead adder. The Booth encoding is performed at the dit level using encoding circuitry implemented in N-NARY logic.

1-of-4 multiplier

An apparatus and method that perform partitionable carry-lookahead logic on two N-nary operands. The operands may be selectably partitioned into 8-bit, 16-bit, 32-bit, or 64-bit operands. The present invention performs carry-lookahead logic to calculate a block carry-lookahead indicator for a grouping, or block, of bits. The present invention forces the block indicator to a &ldquo;Halt&rdquo; value if the block comprises the most significant block within a partition, thus interrupting the carry propagation chain on partition boundaries. The present invention supports interruption of the carry propagation chain for both addition and subtraction.

Method and apparatus for interruption of carry propagation on partition boundaries

An apparatus that takes two N-nary operands and selectably performs either addition or subtraction on them to produce an arithmetic result and a carry indicator. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands and also to create &ldquo;block&rdquo; HPG indicators for blocks of dits. In the preferred 1-of-4 embodiment, subtraction may be implemented as four's complement addition. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit.

Method and apparatus for 3-stage 32-bit adder/subtractor

The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate. The phase of an individual local clock signal overlaps an earlier phase local clock signal by an amount approximately equal to the overlap of the phase of the next individual local clock signal. The first dynamic logic gate, the intermediate dynamic logic gate(s), and the last dynamic logic gates couple such that an individual dynamic logic gate with an individual local clock signal and phase may only provide a signal to the next individual dynamic logic gate that uses a next phase local clock signal where the gates may couple together in series, in a feed back loop, or a feed forward loop.

Method and apparatus for logic synchronization

The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.

Method and apparatus for an N-NARY logic circuit

The present invention allows the logic state of a clocked precharge (CP) logic gate to be tested when stopping or starting the logic gate's clock and comprises a plurality of clock signals with overlapping phases and a plurality of CP logic gates coupled in series. Each CP logic gate of the plurality of CP logic gates is coupled to an individual clock signal. The present invention further comprises one or more signal keeper devices coupled to certain individual CP logic gates in the critical path of the logic state. The signal keeper device allows the state of the plurality of CP logic gates to be tested when stopping or starting the individual clock signal of an individual logic gate of said plurality of logic gates. The present invention is suitable for a variety of testing techniques that includes IDDQ, scan testing, and hardware emulation testing.

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Austin, TX, United States of America

Anthony M Petro