International Business Machines Corporation

Maximus Technologies

Anthony M Palagonia

Bernadette Ann Pierson

Dennis A Schmidt

Patricia E Marmillion

John Edward Cronin

Richard James Evans

Paul Joseph Pikna

John Thomas Maddix

Wayne John Howell

Howard L Kalter

James Marc Leas

Harold G Linde

David P Vallett

Cuc Kim Huynh

Matthew J Rutten

Ronald Jay Bolam

Bruno Roberto Aimi

Patricia McGuinnes Marmillion

Andre Conrad Forcier

Sebastian Theodore Ventrone

Scott Whitney Gould

David Lewis Gardell

Patricia McGuiness Marmillion

Gordon M Babson

Patricia McGuinness Marmillion

Stuart K J Smyth

An emergency stairwell for a building having multiple floors comprising: at least one landing associated with each the floor, each landing increasing in width in at least one horizontal direction from an uppermost landing of an upper floor to a lowermost landing of a lower floor; and at least one set of stairs extending between adjacent pairs of landings.

Emergency stairwell for multistory buildings

Redundant chip sections held in standby are substituted for chip sections that are at risk of over heating based on certain sensor signals. When these signals are received operations of the chip section at risk IS transferred to a redundant chip section and the chip section at risk is shut down. After the original chip section has cooled, it becomes available as a replacement chip section itself. The sensor signals may be based on temperature values, elapsed operation time, and number or rate of operations within a chip section.

Method and apparatus for preventing thermal failure in a semiconductor device through redundancy

A monolithic probe having an integral fine probe point, pressure spring, conductive line, and connector for contacting semiconductor devices to be tested and a method of construction of said probe is described. Integration of a serpentine spring into the probe body reduces breakage and improves contact reliability. Standard, coaxial, triaxial, and Kelvin probes are described. The methods of construction described utilize standard semiconductor processes. The probes may be fabricated to very small dimensions.

Micro probe and method of fabricating same

An electrically activated fuse with a high melting point heater element in series with a low melting point fusible link. The heater element has a higher resistivity and larger cross-sectional area than the fusible link in order to withstand heat that the heater element generates bringing the fusible link to its melting point. Fuse dimensions (width and length) are each between 0.1 and 2.0 microns, with a thermal mass of the heater element being sufficient to melt the fusible link.

Micro fusible link for semiconductor devices and method of manufacture

In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.

Cooling method for silicon on insulator devices

A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial growth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps subdivide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

Method for fabrication of silicon on insulator substrates

A multi-probe ring assembly including integral fine probe tips, conductive lines with terminal connection for testing semiconductor devices and a method of construction of the multi-probe ring assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe points. Semiconductor machining processes are used to complete the probe ring assembly.

Micro probe ring assembly and method of fabrication

A method for forming a silicon on insulator region on a single crystal silicon substrate, comprising the steps of: forming a first dielectric region in a silicon substrate by etching, deposition, and chemical-mechanical polishing; forming a single crystal layer on the substrate by polysilicon deposition and re-growth or epitaxial grownth; removing portions of the single crystal layer to produce silicon islands that are fully on the first dielectric region; and filling in the spaces between the silicon islands with a second dielectric, by deposition and chemical-mechanical-polish, that overlaps peripheral portions of the first dielectric. Additional steps sub-divide the fully isolated silicon on insulator regions by etching trenches in the islands and backfilling with a third dielectric, by deposition and chemical-mechanical-polish.

An interposer for making a penetrating temporary contact between the contact pads of a chip having bumped or unbumped I/O pads and a test board for the purpose of testing said chip is disclosed. The interposer comprises a silicon substrate having sharp penetrating structures integrally formed at a predetermined depth in the silicon substrate along crystallographic planes. The resultant apparatus has a matching lateral thermal expansion to the chip being tested and provides uniform contact to all chip I/O pads.

Method for forming an interposer for making temporary contact with pads of a semiconductor chip

Disclosed is a method and apparatus for polishing a semiconductor wafer. This invention describes a novel in situ method for eliminating residual slurry and slurry abrasive particles on the wafer. A reactant is added to the slurry during the end of the Chemical Mechanical Polish (CMP) process to dissolve the slurry and etch the abrasive particles.

Apparatus for removing slurry particles

A structure (and method) for selectively making an electrical connection comprising a conductive element, wherein the conductive element becomes non-conductive after application of radiation energy, and a reflective element, positioned adjacent at least two sides of the conductive element for reflecting the radiation energy.

Laser fusible link

A probe assembly including an integral fine probe tip, conductive line with terminal connection for testing semiconductor devices and a method of construction of the probe assembly is described. The method of construction described utilizes the step of etching pits into silicon wafers to produce molds for forming the probe point. Semiconductor machining processes are used to complete the probe assembly.

Micro probe assembly and method of fabrication

A heat dissipation apparatus for cooling one or more electronic devices. The apparatus utilizes a moving heat sink a portion of which is in contact with the device to be cooled. The moving heat sink may be in the form of a rotating disk, moving belt or strip. The heat sink may be made from various materials such as metals or plastics.

Method and apparatus for cooling an electronic device

A semiconductor device which includes a first semiconductor chip mounted on top of a lead frame which is molded within a plastic body. During the molding process a cavity is formed on the bottom of the lead frame. After testing or burn-in of the first chip a second semiconductor chip is mounted and electrically connected to the lead frame. The second chip may then be sealed within the cavity to form a multichip module.

Growing community of inventors

Underhill, VT, United States of America

Anthony M Palagonia