Intel Corporation

Anthony M Constantine

Prashant Sethi

Robert J Royer, Jr

Xiang Li

Andrew Warrack Morning-Smith

Myron Loewen

Tawfik M Rahal-Arabi

Bilal Khalaf

Jingbo Li

Konika Ganguly

Daniel Willis

Rebecca Z Loop

Chang-Wu Yen

Yu-Liang Shiao

Myron D Loewen

Deniel S Willis

Examples include techniques for dynamically modifying a platform form factor of a mobile device. In some examples, a system may include a split memory array having a first memory within a docking system and a second memory element within a small form factor (SFF) mobile device. A platform form factor determination component may dynamically select between multiple platform form factors based on a determination that the SFF mobile device is coupled with the docking system. An interface logic component may access the first memory storage of the docking system during a memory (e.g., graphics) computation when the mobile device is physically and electrically/communicably coupled with the docking system to allow the SFF mobile device to have full LFF functionality. When the SFF mobile device is disconnected from the docking system, the interface logic component may access only the second memory storage of the SFF mobile device to provide SFF functionality.

Techniques for dynamically modifying platform form factors of a mobile device

Provided are devices, systems and methods relating to controller interactions with storage. One embodiment includes an apparatus comprising a controller for communication with a storage device through a signal line, wherein the controller is configured to detect a first signal on the signal line indicating the presence of the storage device on the signal line, and provide a second signal on the signal line to reset the storage device after a detection that the first signal indicates the presence of the storage device. Other embodiments are described and claimed.

Combining presence detect pin with device management bus reset and power disable

Provided are an apparatus, system, and method relating to detecting, during a system boot operation, whether a device arranged to implement a first bus interface protocol is coupled to a system through a connector. A bus clock is programmed to be off in response to detection of no device implementing the first bus interface protocol being coupled to the system through the connector. After the bus clock is programmed to be off, a buffer is reprogrammed to assume that the connector implements a second bus interface protocol coupled to a storage device. After reprogramming the buffer, the apparatus, system, and method detect whether a device arranged to implement the second bus interface protocol is coupled to the connector, and the device arranged to implement the second bus interface protocol is initialized in response to detection that the device is coupled to the connector. Other embodiments are described and claimed.

Multiple storage devices implemented using a common connector

Provided are apparatus, system, and method for positionally aware device management bus address assignment. A presence of a plurality of storage devices is detected on a bus. One of the storage devices detected on the bus is selected. A get identifier command is sent on the bus to all of the storage devices that is only responded to by the selected storage device. A unique identifier is received from the selected storage device over the bus. An address for the selected storage device is assigned and an entry is added to the address mapping to indicate the unique identifier, the assigned address, and a physical location indicator for the selected storage device.

Apparatus, system, and method for positionally aware device management bus address assignment

An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower package. One of the packages contain memory devices of a first type and the other of the packages contain memory devices of a second type. I/O connections on the underside of the upper package's substrate are vertically aligned with their corresponding, first I/O connections on the underside of the lower package's substrate. The first I/O connections are located outside second I/O connections on the underside of the lower package's substrate for the lower package.

I/O layout footprint for multiple 1LM/2LM configurations

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Portland, OR, United States of America

Anthony M Constantine