3com Corporation

Anthony Liem Pan

Burton B Lo

Marwan A Fawal

Richard S Reid

Eric Roger Davis

George Kwan

Krishna Uppunda

Pauline Cheng

Maria B Hu

An integrated circuit is provided to convert an analog telephone signal into a digital format. The integrated circuit includes an analog-digital converter coupled to an averager. Sampled analog values are averaged at intervals and compared to a threshold level to determine a digital value.

Telephone network signal conversion system

A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority , priority , . . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain. In one embodiment, timers regulate the transmission of isochronous packets. The arbiter transmits the isochronous packet, if any, with the timer and otherwise allows the next stage a transmit turn. The next stage checks if a priority packet is present and if a priority packet was not sent the last time its turn was reached. If yes, the priority packet is sent, if not, then the above decision is repeated with respect to the next lower priority circuit stage. Priority arbitration improves quality of service performance.

Scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card

A system for reducing electromagnetic interference emissions is described. The system can include a network interface card with an Ethernet controller circuit. The Ethernet controller circuit generates an Ethernet output signal that includes a pre-emphasis component and a data component. The Ethernet controller circuit monitors the Ethernet output signal and adjusts the levels of the pre-emphasis component and the data component to reduce the electromagnetic interference caused by the network interface card but still fit the requirements for valid Ethernet signals.

System and method to reduce electromagnetic interference emissions in a network interface

A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple discrete circuit components. The invention incorporates a method and apparatus that will minimize subsystem latencies and inefficiencies in order to maximize data throughput and system performance. In yet another embodiment, the RISC processor interface bus is the AMBA ASB bus. The invention further provides an Advanced RISC Machine interface bus unit which uses an improved clock crossing handshake mechanism that can support a range of clock frequencies on the AMBA ASB bus.

Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus

A slave interface circuit for providing communication between a PCI (Peripheral Component Interconnect) bus domain and an ASB (Advanced System Bus) bus domain. The novel circuit is an integrated interface for communicating using the AMBA (Advanced Microcontroller Bus Architecture) ASB protocol and translating ASB commands into PCI like commands. Embodiments include interfaces that are particularly suited for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) implementations. A high-speed embodiment is also discussed allowing prefetch functionality. Input latches catch ASB commands on the falling edge of the ASB clock and then circuits reformat the data using size information and address bits from the ASB bus. This allows byte, halfword and word accesses. Byte readback data are provided on all four byte lanes and halfword readback data are provided on both halfword lanes. The reformatted data is latched into a set of request registers on the next rising edge of the ASB clock. During an ASB read request, the read data is latched on the rising edge of the ASB clock such that the ASB master agent can latch its requested data on the next falling edge of the ASB clock. The other handshake signals are latched on the falling edge of the ASB clock. An ASB master agent can sense the handshake on the rising edge of the ASB clock. Pipeline architecture allows the bus protocols to operate at optimum speed and supports the natural flow of data between the ASB and PCI domains without the need for wait cycles. Pipelined ASB burst cycles are supported.

Slave interface circuit for providing communication between a peripheral component interconnect (PCI) domain and an advanced system bus (ASB)

A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full. An analogous process operates for the Rx FIFO entry point. Providing a queued entry point reduces processor utilization and PCI bus utilization in communicating packets with the network because memory pointers can be directly pushed onto the transmit FIFO by the processor without encountering race conditions. Providing a queued entry point also increases NIC efficiency by avoiding processor initiated NIC stalls. Both improve quality of service performance.

FIFO queued entry point circuit for a network interface card

NMOS transistor buffers are used to buffer the output of a system. The system can include a network interface card. The NMOS transistor buffers receive the output of the shaped Ethernet data signals and drive a transformer. The NMOS transistor buffers allow for low power consumption while a feedback monitoring system provides stability by controlling the inputs to the NMOS transistors.

Low power buffer system for network communications

A method for efficient data transfers between domains of differing data formats. In one exemplary implementation, data transfer is performed with respect to an IEEE 1394 communication domain and an Ethernet communication domain. The novel data transfer method advantageously eliminates the need to copy the data payload section of a received data packet from one memory region to another memory region within a bridge device coupled between first and second communication domains. Specifically, the header, data payload and trailer sections of a received data packet (of a first communication domain format) are copied into a first portion of memory within the bridge device. The present invention then assembles a new data packet by constructing a new header of a second communication domain and appending a pointer to the new header that points to the data payload location within the first portion of memory. The header includes a destination address obtained from the data payload location and a source address of the bridge device. The new packet is of the second communication domain. The bridge device then transmits the new header section to the second communication domain and forwards the data payload therewith using the pointer as a reference. Domain interface controller circuits then add the new trailer, as required, to the new packet. By passing a pointer to the data payload, the present invention eliminates the need to copy the data payload from one region of memory to another during the transfer operation.

Method for efficient data transfers between domains of differing data formats

A method and circuit for handshaking information across multiple clock domains within an electronic system. The environment of the present invention includes an electronic or computerized system having at least two subsystem domains (a first domain and a second domain) operating at different clock rates (a first clock and a second clock). The present invention includes a handshake circuit coupled between the first and second domains for providing the required handshaking signals to control the transfer of data between the first domain (master) and the second domain (slave). An information bus is coupled between the domains. The handshake circuit is such that double synchronization is not required and the design of the present invention is dynamic such that it is operable between clock domains of varying frequency. The present invention utilizes the asynchronous input of a flip-flop circuit to catch the pertinent handshaking signals between clock domains. The D input and the clock input of the flip-flop circuit are coupled to the master clock domain and the master clock domain receives a ready signal back. When ready is asserted, the master domain may assert a request (from the master domain) over the D input and hold data. The Q output is coupled to a request (to the slave domain) which is also coupled as an input to a NOR circuit. An acknowledge signal is coupled to the asynchronous flip-flip input as a clear and also coupled to the second input of the NOR circuit. The output of the NOR circuit generates the ready signal.

Method and circuit for providing handshaking to transact information across multiple clock domains

A method for managing data transfers with minimal host processor involvement. Data is transferred between a peripheral device coupled to a host computer and a network device over a high performance bus. In one exemplary embodiment, data is transferred over a bus utilizing the IEEE 1394 communication protocol and a network utilizing the Ethernet communication protocol. The novel data transfer method advantageously minimizes the involvement of the host computer's processor in the management of data transfers, thus maximizing the host processor's availability for performing other computations. Specifically, to transfer data from the peripheral device to the network, the host processor generates a data pointer table and sends it to the network device. A processor in the network device then takes over data transfer management, using information in the data pointer table to locate and transmit the designated block of data from the peripheral device to the network. In another embodiment, the present invention determines whether the size of a data block to be transferred exceeds the maximum packet size for the relevant communication protocol used by the bus or the network. If such a limit exists and is exceeded, the data pending transfer is divided into multiple packets, such that each packet conforms to the maximum packet size of the limiting protocol. Then, the smaller packets are transmitted iteratively until the entire data block is transferred. As such, the present invention eliminates the incompatibility problem posed by the differences in packet sizes among different communication protocols.

Method for managing network data transfers with minimal host processor involvement

The circuit provides a scaleable buffer coupled between digital domains that require data buffering because they operate at different data transfer rates and/or because one or more of the digital domains uses data bursting. The scaleable buffer circuit does not have a large fixed throughput latency as is characteristic of a first-in-first-out buffer. The buffer includes serially coupled burst cells each having a sequential element, a controlled multiplexer and control logic for controlling the multiplexer and for generating output control signals. In one embodiment, the control circuit is a finite state machine. Each burst cell is capable of receiving data from an upstream burst cell or from the input data bus. Therefore, the buffer can be filled starting from its most downstream and vacant burst cell rather than always starting from the most upstream cell (as in a typical FIFO). This reduces the throughput latency of the buffer in cases when it is not always full. By using burst cells, rather than a dual ported RAM, the interface circuitry is significantly reduced in complexity. Each burst cell is uniform in construction and contains distributed interface circuitry making the circuit readily scaleable in size without redesigning the interface circuitry.

Intelligent scaleable FIFO buffer circuit for interfacing between

A byte accessible memory interface circuit using a reduced set of memory control signals. The present invention includes an interface circuit having a reduced set of memory control signals for performing word length reads and writes to an external memory module containing a plurality of integrated circuit (IC) memory chips. The interface circuit contains a respective multiplexer and a respective register circuit for each byte of the word length data. The multiplexers select a byte of data from either an on-chip data bus or from a bus carrying data read from the external memory module. To perform a full length word write, the data from the on-chip bus is loaded into the registers (via the multiplexers) and then written to the memory module. To perform a partial length word write, a pre-read operation is performed at the target address and a word length data is loaded into the registers. The new data is then received over the on-chip data bus and routed by the multiplexers into the byte locations to be changed. The properly merged data is then written as a full length word to the memory module. To perform a full length word read, a word of data is loaded into the byte registers and then forwarded over the on-chip data bus. By the provision of a pre-read operation, all of the IC memory chips can share the same chip enable, output enable and write enable control signals thereby reducing pin count on the integrated circuit that contains the interface circuit.

Byte accessible memory interface using reduced memory control pin count

One embodiment of the invention includes a transformer that is at least partially formed on a substrate. The transformer is for electrical isolation and signal filtering. The transformer includes the following elements. A portion of the substrate has two holes through the substrate. A ferrite core is formed in a loop through the two holes. A primary winding is made of a first metal trace. The first metal trace is formed in a spiral around one hole. The first metal trace has at least two primary terminals acting as an input to the transformer. The transformer also includes a secondary winding. The secondary winding is made of a second metal trace. The second metal trace is formed in a spiral around the other hole. The second metal trace has at least two secondary terminals acting as an output from the transformer. The parasitic capacitance of the first metal trace and the magnetizing inductance of the primary winding cause signals received at the primary terminals to be filtered as the signals are passed through the transformer to the secondary terminals.

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Fremont, CA, United States of America

Anthony Liem Pan