Intel Corporation

Anthony Jebson

Nigel C Paver

Deli Deng

Mark Norman Fullerton

Stephen J Strazdus

Mukesh Patel

Murli Ganeshan

Wing K Yu

Jianwei Liu

Rupal Parikh

William T Maghielse

Yuyun Liao

Lynn A Comp

Steve J Strazdus

Kailesh B Bavaria

In one embodiment of the present invention, a method includes translating instructions of a code portion from a first instruction set to a native instruction set; and disabling of translating the instructions when a compilation process is ready for execution.

Combining compilation and instruction set translation

A tightly coupled dual 16-bit multiply-accumulate (MAC) unit for performing single-instruction/multiple-data (SIMD) operations may forward an intermediate result to another operation in a pipeline to resolve an accumulating dependency penalty. The MAC unit may also be used to perform 32-bit&#xd7;32-bit operations.

Multiply-accumulate (MAC) unit for single-instruction/multiple-data (SIMD) instructions

A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a target coprocessor for coprocessor instructions. Two bits indicate one of four data sizes including a byte (8 bits), a half word (16 bits), a word (32 bits), and a double word (64 bits). Two other bits indicate a saturation type.

Conditional execution of coprocessor instruction based on main processor arithmetic flags

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Austin, TX, United States of America

Anthony Jebson