Wolfson Microelectronics Limited

Cirrus Logic Inc.

Anthony James Magrath

Richard David Clemow

John Paul Lesso

Jeffrey Donald Alderson

Roberto Napoli

Bryant Sorensen

Clive Robert Graham

John Westlake

The present disclosure relates to a neuron for an artificial neural network, the neuron comprising: a first dot product engine and a second dot product engine. The first dot product engine is operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The second dot product engine is operative to: receive a second set of weights; receive the set of inputs; and calculate the dot product of the set of inputs and the second set of weights to generate a second dot product engine output. The neuron further comprises a combiner operative to combine the first dot product engine output and the second dot product engine output to generate a combined output, and an activation function module arranged to apply an activation function to the combined output to generate a neuron output.

Neurons for artificial neural networks

A noise cancellation system, comprising: an input for a digital signal, the digital signal having a first sample rate; a digital filter, connected to the input to receive the digital signal; a decimator, connected to the input to receive the digital signal and to generate a decimated signal at a second sample rate lower than the first sample rate; and a processor. The processor comprises: an emulation of the digital filter, connected to receive the decimated signal and to generate an emulated filter output; and a control circuit, for generating a control signal on the basis of the emulated filter output. The control signal is applied to the digital filter to control a filter characteristic thereof.

Noise cancellation system with lower rate emulation

Accessing a circular buffer in memory from a processor may be performed with the aid of precomputed values stored in a pointer descriptor field of a processor storage element, such as a register. The pointer descriptor may store a precomputed value for calculating a memory address in the circular buffer, which may include two values, in which the two values are based, at least in part, on the size of the circular buffer, but neither be the size of the circular buffer. The first value may be used to derive a starting memory location for a circular buffer. The second value may be used in combination with the first value to calculate an end memory location. The start and end locations or addresses, along with the precomputed stored values, are then used to calculate the next address based on the current address of a circular buffer in an efficient manner.

Circular buffer descriptor for describing and/or accessing a circular buffer

Methods and systems for thermal protection of a voice coil of a loudspeaker. The method involves driving the loudspeaker based on an input signal received at an input terminal and monitoring both a voltage applied to the voice coil and a current flowing through the voice coil. From the monitored voltage and current, an estimate of temperature of the voice coil and an estimate of power dissipation in the voice coil is determined. The method includes estimating the voice coil resistance based on the monitored voltage and current and at least the estimate of temperature is determined based the estimate of resistance. A gain control signal for modulating a gain applied to the input signal is generated as a function of both the estimate of temperature of the voice coil and the estimate of power dissipation in the voice coil. This means that high power dissipation, which would over long periods lead to overheating, can nevertheless be permitted when the voice coil temperature is low enough, while at high voice coil temperatures any gain modulation applied for thermal protection can be reduced if the power dissipation level drops.

Loudspeaker protection systems and methods

There is provided a noise cancellation system, comprising: an input for a digital signal, the digital signal having a first sample rate; a digital filter, connected to the input to receive the digital signal; a decimator, connected to the input to receive the digital signal and to generate a decimated signal at a second sample rate lower than the first sample rate; and a processor. The processor comprises: an emulation of the digital filter, connected to receive the decimated signal and to generate an emulated filter output; and a control circuit, for generating a control signal on the basis of the emulated filter output. The control signal is applied to the digital filter to control a filter characteristic thereof.

A noise cancellation system for an audio system such as a mobile phone handset, or a wireless phone headset has a first input for receiving a first audio signal from one or more microphone positioned to receive ambient noise, and a second input for receiving a second audio signal from a microphone positioned to detect the user's speech, as well as a third input for receiving a third audio signal for example representing the speech of a person to whom the user is talking. A first noise cancellation block receives the first audio signal and generates a first noise cancellation signal, and this is combined with the third audio signal to form a first audio output signal. A second noise cancellation block receives at least a part of the first audio signal and said second audio signal and applying noise cancellation to generate a second audio output signal.

Noise cancellation system

An infinite impulse response (IIR) filter is provided for receiving an input signal and outputting a filtered signal. The filter comprises feedback circuitry for feeding back said filtered signal, the feedback circuitry comprising a first delay element for delaying said filtered signal; and a sub-unit, for receiving said delayed filtered signal, for outputting a summed signal which is the difference between said delayed filtered signal and a further-delayed filtered signal, and for outputting a multiplied signal which is an inverted further-delayed filtered signal multiplied by a first filter coefficient. At least said input signal, said delayed filtered signal, said multiplied signal, and said summed signal are employed to generate said filtered signal.

IIR filter for reducing the complexity of multiplying elements

A circuit for preventing clipping in an Automatic Level Control (ALC) or Limiter, where the amplitude of the signal above the clipping point is estimated, then the signal level is automatically reduced over a defined period substantially equal to the feedforward delay in the ALC/Limiter. By adaptively controlling, based on the excess amplitude and the delay time available, an attack rate used in the ALC/Limiter to reduce the gain applied to an input signal, it can be ensured that the output amplitude is brought within the clipping level sufficiently quickly to prevent audible clipping.

Dynamic range controller

An amplifier circuit () has an input stage (OP) and an output stage (Q, Q) operating with different supply voltages and different quiescent voltages. The output stage has a feedback input connected to receive a feedback signal from the output of the output stage. A biasing circuit () applies a bias signal (Ioff) to said input stage at an operating level appropriate to establish a quiescent output voltage different from a ground reference level of the input stage. To start up the amplifier with minimal transients at the output, the following steps are performed in sequence: (a) with the output stage disabled, pre-charging the amplifier output over a period of time to a level (Vmid) corresponding to the ground reference level of the input stage; (b) with the biasing circuit effectively disabled and a zero input signal at said signal input, enabling the input and output stages; (c) activating said biasing circuit progressively so as to ramp said bias signal (Ioff) to said operating level over a further period of time, thereby driving the output progressively to said quiescent output voltage. A separate improvement is in the biasing circuit, which uses the actual output stage supply voltage (PVdd) as a reference to define the operating level of said bias signal (Ioff).

Amplifier circuits, methods of starting and stopping amplifier circuits

A sample rate converter circuit receives a first signal at a first sampling frequency and for outputs a second signal, representative of the first signal, having a second sampling frequency. The sample rate converter comprises: a buffer, for storing data samples received from said first signal; a first loop circuit, for receiving a first clock signal corresponding to the first sampling frequency and a second clock signal corresponding to the second sampling frequency, and for generating an estimate of a ratio of the first sampling frequency to the second sampling frequency; and a second loop circuit, for receiving the first clock signal, the second clock signal and the estimate of the ratio of the first sampling frequency to the second sampling frequency, and for outputting a write pointer so that the data samples can be stored in the buffer, and for outputting a read pointer so that the data samples can be read from the buffer, with a first offset between the read pointer and the write pointer, such that the first offset is substantially independent of the ratio of the first sampling frequency to the second sampling frequency.

Sample rate converter

A digital-to-analog converter having an input for receiving a digital input signal during each time period. A plurality of elements are each adapted to produce an analog output in response to an input, and an encoder selects a number of the elements and applies inputs to the selected elements. An analog output signal is then formed by summing outputs of the plurality of elements. The encoder selects the number of elements based on a value of the digital input signal, and selects the elements in a predetermined order from the plurality of elements, starting from an element determined by the elements selected in an immediately preceding time period, and excluding a temporarily omitted one of the plurality of elements.

Digital-to-analog converter using selected single bit converter elements

In a dynamic element matching stage of a digital-to-analogue converter, in which a pair of quantizer outputs are generated, and are constrained such that their sum is equal to the parity of a received bit value, steps are taken to improve baseband noise performance. Each of the quantizers has a feedback loop associated with it, and the performance is improved by determining the quantizer outputs based on these loop values, in order to reduce the overall quantization noise. However, during time periods when these loop values are equal, there are two possible pairs of quantizer outputs that could be chosen, without adversely impacting on the overall quantization noise. the quantizer outputs are monitored during such time periods, and steps are taken to control the quantizer outputs during such time periods, in order to ensure that the two possible pairs of quantizer outputs are chosen with equal probability.

Digital-to-analog converter with dynamic element matching to minimize mismatch error

The present invention relates to audio signal processing such as equalisation and spatial enhancement functions. The present invention provides an audio signal processing circuit arrangement for two audio channels, and which combines spatial enhancement or acoustic mixing (crosstalk) cancelling with graphic equalisation functions. This is achieved with a circuit structure having a reduced filter count compared with known cascaded circuits dedicated to each function. The circuit structure processes the sum and difference signals through separate filters and then recombines them to recover the separate channels (adding and subtracting respectively).

Growing community of inventors

Edinburgh, United Kingdom

Anthony James Magrath