Teradyne, Inc.

Genrad, Inc.

Other

Anthony J Suto

John Joseph Arena

Joseph Francis Wrinn

Alexander H Slocum, Jr

John P Toscano

Charles P Smith

Michael W Hamblin

Jason A Messier

Moses Khazam

Bradley A Phillips

Karl Karash

R Scott Ziegenhagen

Peter J D'Antonio

Fadi H Daou

Kyle L Klatka

Jak Eskici

John D Moniz

Brian L Massey

Robert J Muller

Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

Method and apparatus for bond wire testing in an integrated circuit

An example process includes: powering, via a power supply, an active-matrix display panel comprised of picture elements; and identifying, based on an output of the power supply, one or more picture elements in the active-matrix display panel that are potentially defective. The example process may also include identifying, among one or more of the picture elements that are potentially-defective, one or more picture elements that actually are defective.

Identifying potentially-defective picture elements in an active-matrix display panel

An example test fixture, which interfaces a tester and a unit under test (UUT), includes the following: first electrical contacts that face the tester; second electrical contacts that face the UUT; a substrate made of sections of printed first material, with the first material being electrically non-conductive, and with the substrate being between the first electrical contacts and the second electrical contacts; and structures through the substrate, with the structures including sections of second material, with the second material being electrically conductive, and with at least one of the structures electrically connecting a first electrical contact and a second electrical contact.

Test fixture

A probe assembly for capacitive testing electrical connections of a low profile component to a circuit assembly. The probe assembly is configured to reduce coupling of noise signals from the circuit assembly to the capacitive probe. The probe assembly includes a sensing member with a geometry that allows the probe to preferentially couple to test signals from the pins of a component under test rather than conductive structures on the circuit assembly, such as pads, and signal traces to which those pins are attached. The sensing member may be a vertical capacitive sense plate such that coupling is to an edge of the plate. The sensing member alternatively may be a horizontal capacitive sense plate with an active area of the probe surrounded by an isolation ring. Measurements made with such capacitive probes may provide test measurements that yield a reliable discrimination between a properly attached pin and an open pin.

Capacitive opens testing of low profile components

A test system and method for identifying open and shorted connections on a printed circuit board (PCB). An integrated circuit (IC) unit on the PCB is configured to generate a test signal on an output pin connected to a test pin on a second device, connector, or socket on the PCB. For a connection, the test signal is capacitively coupled to a detector plate proximal the second device. Based on the signal coupled to the detector, time domain analysis is performed on the coupled signal to determine if the test pin has a good connection to the PCB or if the pin is open or shorted. Analysis may include cross-correlating the coupled signal with a learned signal obtained from a known 'good' PCB. The test pin may pass the test if the cross-correlation is within a specified threshold window. If the test fails, additional tests may be performed to troubleshoot the cause of the testing failure.

Method and apparatus for testing electrical connections on a printed circuit board

An example system for testing electronic assemblies (EAs) may include carriers for holding EAs and slots for testing at least some of the EAs in parallel. Each slot may be configured to receive a corresponding carrier containing an EA and to test the EA. An example carrier in the system may include a first part and a second part. At least one of the first part and the second part include a first structure, and the first structure is movable to enable electrical connection between an EA and an electrical connector.

Electronic assembly test system

A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second signal, out-of-phase with the first signal, is applied to a second group of pins associated with the component. The amplitude and/or the phase of the second signal and the number and/or specific pins in the second group of pins are selected so that first and second signals coupled to a detector plate proximal to the component substantially offset. During a manufacturing test, signals of comparable amplitude and phase are applied to like pins on a like component of a circuit assembly under test. If the response signal coupled to a like detector plate is below a threshold, it is determined that each pin in the group of parallel connected pins is connected. If the amplitude of the response is over the threshold, one or more of the parallel pins is determined to be open. Additional tests may be performed to identify which of the parallel pins is likely open.

Fast open circuit detection for open power and ground pins

An improved system for capacitive testing electrical connections in a low signal environment. The system includes features that increase sensitivity of a capacitive probe. One feature is a spacer positioned to allow the probe to be partially inserted into the component without contacting the pins. The spacer may be a collar on the probe that contacts the housing of the component, contacts the substrate of the circuit assembly, or both. In some other embodiments, the spacer may be a riser extending beyond the surface of the sense plate that contacts the component, a riser portion of the component, or a combination of both. The spacer improves sensitivity by establishing a small gap between a sense plate of the probe and pins under test without risk of damage to the pins. A second feature is a guard plate of the probe with reduced capacitance to a sense plate of the probe. Reducing capacitance also increases the sensitivity of the probe.

Low capacitance probe for testing circuit assembly

A test system for testing a unit such as multiple solid oxide fuel cells. The test system includes a thermal test chamber in which a non-contact electrostatic voltage probe is mounted to scan the solid oxide fuel cells. The test system includes a detector coupled to the voltage probe to produce an output signal or display based on the measured voltages. The measured voltages are processed to compute a representative voltage for each fuel cell and to identify any defective fuel cells based on the measured voltages. The test system may be used during manufacture of solid oxide fuel cell stacks for cost effective testing to lower manufacturing costs.

Identifying fuel cell defects

A reliable and durable method of testing of printed circuit boards is presented. Test access components are placed in contact regions for providing electrical connectivity between test probes and the printed circuit board. In some cases, a test access component may be a surface mount resistor. The test access component may provide two points of contact for test probes to make electrical and mechanical contact with the printed circuit board. Test access components may also provide for increased durability of testing, allowing for a greater number of test contacts to be made between test probes and printed circuit boards than were previously possible.

Test access component for automatic testing of circuit assemblies

Capacitive opens testing in low signal environments

Pin-driver circuitry in each of an automatic circuit tester (,)'s digital driver/sensor circuits (,) includes a current sensor (R,, QS,QS,D,and D,) and comparison circuit (,) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT_VALUE). The pin-driver circuitry also includes a timer (,) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME_VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate. When no backdriving is sensed during a given burst of test signals, the tester forgoes the normal cool-down delay, thereby speeding the test process.

Circuit-board tester with backdrive-based burst timing

Pin-driver circuitry in each of an automatic circuit tester (10)'s digital driver/sensor circuits (36) includes a current sensor (R.sub.sense, QS1, QS2, D1, and D2) and comparison circuit (58) that indicate whether the load current supplied by the driver exceeds a level set by a threshold input (CURRENT.sub.-- VALUE). The pin-driver circuitry also includes a timer (60) whose output indicates whether the comparison circuit's output has been asserted for a length of time that exceeds a limit set by a duration input (TIME.sub.-- -VALUE). When it has, the tester disables the driver and thereby prevents damage that could otherwise result from excessive backdrive durations that the test-generation process did not anticipate.

Direct-measurement provision of safe backdrive levels

An output circuit (62) for generating a signal in the form of a voltage between an output signal node and an output reference node (60) receives power from a pair of voltage regulators (Q1 and 68, Q2 and 70). The regulators are connected in power-circuit series so as to be powered by the difference between the output potentials of two opposite-polarity supplies without a direct low-impedance connection between the power-supply ground (73) and the output reference node (60). To avoid large current flow in any external path between an output reference node (60) of an electronic circuit and the ground node (73) of its power supply, a current sensor (R1, R2, 86) senses the net current that the power supplies provide to the circuitry that includes the regulators, and it controls variable loads (Q3, Q4) that selectively drive current into and draw current from the reference node (60) so as to drive the net current to zero.

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Sterling, MA, United States of America

Anthony J Suto