International Business Machines Corporation

Anthony J Perri

Sebastian Theodore Ventrone

Pascal A Nsame

Richard C Jordan

John J Ellis-Monaghan

Mark David Jaffe

Richard John Rassel

Charles Joseph Masenas

Mete Erturk

Mark Steven Styduhar

Ezra D B Hall

Theodoros Anemikos

Emory D Keller

Tian Xia

Troy A Seman

Karl H Hoppe

Robert J Gallagher

Lansing D Pickup

Phillip L Corson

Barton E Green

Jordan M Taylor

Paul Scot Carlile

Sambasivan Narayan

Bert W Weidle

Lansing U Pickup

Matthew R Welland

Matthew R Walland

Robert C Jordan

Disclosed are embodiments of a system and a method that allow for wireless and dynamic intra-process (i.e., during and/or between process steps) measurements of integrated circuit parameters. The embodiments incorporate the use of a passive circuit, such as an inductor-capacitor-resistor (LCR) circuit resonator, that has a predetermined sensitivity to process variations in one or more physical or electrical integrated circuit parameters. The passive circuit can be wirelessly interrogated between and/or process steps. Then, the actual behavior exhibited by the passive circuit in response to the interrogation is compared to the expected behavior of an optimal circuit in the absence of process variations in order to determine the one or more parameters. Also disclosed is an embodiment of an exemplary passive circuit that can be used to implement the disclosed system and method embodiments.

System and method for wireless and dynamic intra-process measurement of integrated circuit parameters

The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Structure for dynamic latch state saving device and protocol

A semiconductor die including a semiconductor chip and a test structure, located in a scribe area, is designed and manufactured. The test structure includes an array of complementary metal oxide semiconductor (CMOS) image sensors that are of the same type as CMOS image sensors employed in another array in the semiconductor chip and having a larger array size. Such a test structure is provided in a design phase by providing a design structure in which the orientations of the CMOS image sensors match between the two arrays. The test structure provides effective and accurate monitoring of manufacturing processes through in-line testing before a final test on the semiconductor chip.

Image sensor monitor structure in scribe area

An asynchronous data transfer interface is provided across a boundary that allows high bandwidth data transfers which are packet based as defined by PCI_Express architecture, and has general utility in processor-based applications like servers, desktop applications, and mobile applications. A shared set of multi-port RAM buffers allow both an application layer AL and a transaction layer TL access to a communication protocol layer in a defined process that allows both the application layer AL and the transaction layer TL to read and manage the buffers in a 16 byte boundary in a manner that allows a data credit to be decoupled from a header credit.

Asynchronous packet based dual port link list header and data credit management structure

The invention comprises a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated to said charge device, a data signal output distributed from the charge device, and a clock signal allotted to the charge device, wherein said integrated recovery mechanism maintains a state of the charge device independent of the charge device.

Dynamic latch state saving device and protocol

A phase- or frequency-locked loop circuit () that generates an accurate output signal (ACC_SYN_OUT) even in the presence of edge-triggering-type glitches (A,B) in the input reference clock signal (REF_CLK). The locked-loop circuit includes a phase or frequency difference detector () and a glitch detector () that generates a trigger signal (GLITCH_DETECTED) upon detection of at least one glitch. The trigger signal resets the difference detector so as to abort the updating of the output signal that the glitch would otherwise cause.

Phase- or frequency-locked loop circuit having a glitch detector for detecting triggering-edge-type glitches in a noisy signal

A variable-frequency digital ring oscillator provides small and consistent frequency adjustments throughout a locked range. The ring oscillator of the invention is standard cell placeable and operates at the technology limits to provide small and precise delay changes that is inexpensive to implement. The digital variable-frequency ring oscillator includes multiple macro delay elements forming an inverter ring circuit, each element having an individual macro delay unit that in turn is comprised of multiple adjustable delay units. All of these adjustable delay units are controlled by a single delay control signal.

Ring oscillator with adjustable delay

A frequency synthesizer includes a charge pump, a fractional integration counter that alters the integrated current of the charge pump, a phase frequency detector, a proportional correction circuit, and a proportional multiplier that alters the value of the current correction output by the proportional correction circuit. The fractional integration counter alters the integrated current of the charge pump based upon a user-defined input, thereby permitting increased signal-to-noise ratio at the output of the charge pump. Similarly, the proportional multiplier alters the value of the proportional current correction based upon user-defined input, thereby modifying loop dynamics within the frequency synthesizer.

Fractional integration and proportional multiplier control to achieve desired loop dynamics

A digitally controlled oscillator includes an adjustable signal generating circuit adapted to generate an oscillation signal. A feedback loop receives the oscillation signal from the adjustable signal generating circuit. The feedback loop detects error in the oscillation signal and produces an error signal based on the error. The control logic circuit receives the error signal from the feedback loop and maintains the oscillation signal within a predetermined error range. Also, a state device that is connected to the adjustable signal generating circuit maintains a previous operating state of the adjustable signal generating circuit when the digitally controlled oscillator is temporarily powered down. When the digitally controlled oscillator is powered up after being temporarily powered down, the control logic starts the adjustable signal generating circuit at the previous operating state based upon data maintained within the state device, and restarts the feedback loop and error processing circuits in a way to avoid oscillator adjustments based on old data.

Digitally controlled oscillator with recovery from sleep mode

An inexpensive and low power consumption power control unit that does not require a separate interface or network. In the power off state only a detector and a power controller require power, this power is supplied from a power source. Upon detection of traffic a frame decoder is powered up to receive frames. When the link is quiet, the decoder is powered down while the power controller and receiver remain powered and await further traffic.

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Jericho, VT, United States of America

Anthony J Perri