Cirrus Logic Inc.

Centillium Technology

Anthony J O'Toole

Shahin Hedayat

Sriraman Chari

Shrikant Acharya

John A Wishneusky

Bhoopal R Benjaram

Surendra Babu Mandava

Cecil Kaplinsky

Guozhu Long

Pulp-insulated telephone cables common in Japan and other countries have higher cross-talk interference than plastic-insulated cables common in the United States. Deployment of newer xDSL systems in Japan has been limited by the high cross-talk interference in those pulp cables, especially the near-end cross-talk (NEXT) from ISDN services using time-compression multiplexing (TCM). A TCM-DSL that can share pulp-cable bundles with TCM ISDN lines eliminates the NEXT interference by synchronizing transmission and reception with the TCM ISDN equipment for the same cable bundle. The TCM-DSL line uses TCM that is synchronized with the ISDN transmit and receive windows so that the TCM-DSL is transmitting but not receiving when the ISDN modems at the same side are transmitting. When ISDN at the same side are receiving and not transmitting, NEXT interference does not exist. Thus higher-speed TCM-DSL data can be received during the ISDN receive windows with reduced interference. A passband modulation technique such as Carrierless-amplitude/phase modulation (CAP) with advanced signal processing techniques such as trellis encoding and pre-coding achieve higher data rates for TCM-DSL. The TCM-DSL transmitted signal occupies a pass-band that is separate from a low-frequency POTS band for voice-band services. The voice calls use full-duplex continuously without regard to the TCM-DSL data transmitted simultaneously with the POTS voice calls over the same phone line. TCM-DSL is synchronized to an ISDN clock that is routed to the TCM-DSL line card, or a burst-timing extractor that detects burst timing from either the ISDN line signal or cross-talk from the ISDN line signals.

Time-multiplexed transmission on digital-subscriber lines synchronized

An integrated line-card terminates an asymmetric digital-subscriber line (ADSL) copper-pair at a single point in a central office. The line card contains analog line circuitry such as a ring generator, off-hook detector, D.C. current feed, and a single analog-digital (A/D) converter. The phone line carries a composite signal of both the high-frequency ADSL data and the low-frequency voice or plain-old-telephone-service (POTS) signal. Instead of using an analog frequency-splitter with bulky, expensive inductor coils, a digital splitter is used. A digital-signal processor (DSP) can be used to perform the digital splitting of ADSL and POTS. The waveforms from the analog phone line are first converted to digital values by the A/D converter, and then a digital splitter separates the low-frequency POTS from the high-frequency ADSL. The ADSL data is formatted by the DSP for a data pathway to the Internet, while the POTS data is converted by the DSP to A-Law or C-Law for transmission over the telephone network's PCM highway. The DSP can perform all decoding, encoding, compression, and formatting needed by both ADSL and POTS. The quality of the phone line is improved by having a single termination point at the central office, rather than separate termination points for POTS and ADSL data from the phone line.

ADSL integrated line card with digital splitter and POTS CODEC without

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which descriptors of data buffers are stored in a circular descriptor queue. The descriptors of those data buffers that are currently available for use in a DMA transfer are maintained in contiguous locations in the descriptor queue. The location of the first available descriptor and the number of currently available descriptors in the descriptor queue are provided to a network controller. Based on this information, the network controller then obtains a set of available descriptors and fills the corresponding buffers with data as it arrives on the different channels. When the use of a data buffer in a DMA transfer is complete, the descriptor for this buffer is made available again in the descriptor queue by re-filling this descriptor immediately following the available descriptors. No matter in which order the individual channels of the multi-channel system use and return the data buffers, the available descriptors are maintained in contiguous locations in the descriptor queue, increasing the efficiency of the system since searching through the descriptor queue for available descriptors is not required.

System for managing direct memory access transfer in a multi-channel

A method and apparatus of managing a multi-channel direct memory access (DMA) operation in which a sequence of data frames are received at a controller that controls a DMA transfer. The data frames are placed in data buffers in a memory by the controller. Multiple data frames are stored by the controller in at least one of the data buffers. The storing of multiple data frames in a single buffer provides efficient utilization of memory space as large size buffers are used to hold more than a single data frame, and also reduces the management overhead involved in placing the data frames in the data buffers.

Method and apparatus for placing multiple frames of data in a buffer in

A combined BAUD rate generator and digital phase locked loop (DPLL) circuit operates in either an asynchronous BAUD rate generating mode or a synchronous phase-locked mode. The combination circuit requires less circuitry than a functionally equivalent circuit with a separate BAUD rate generator and DPLL. The combination circuit comprises a count register, a period register, a decrementing/incrementing circuit, a phase adjusting circuit, and a clock option register. In a first operating mode, the combination circuit functions as a programmable BAUD rate generator which may be used for asynchronous communication applications. In a second operating mode, the combination circuit functions as both a programmable BAUD rate generator and a digital phase locked loop that may be used for synchronous communication applications and that includes an improved method for phase locking a sampling signal to an input signal. The combination circuit utilizes the same period register, count register, clock option register, and other common circuitry, during both the BAUD rate generating mode and the phase locked mode.

Combined BAUD rate generator and digital phase locked loop

This invention provides a flexible, general-purpose, engine-based architecture for a multi-channel data communications controller. It can be customized to handle a wide range of protocols and other host system requirements with minimal reliance on the host's processing power. The always present time-critical tasks of transmitting and receiving serial data, as well as transmitting and receiving characters to/from the host, are handled quickly and efficiently by utilizing dedicated interface processors. This leaves the general purpose main engine less burdened with these time cricital tasks, enabling it to perform the relatively more complex (though less time critical) tasks of assembling and disassembling characters, as well as maintaining RAM-based data FIFOs and performing error-checking and other protocol-related tasks. Custon protocols can be implemented merely by re-microcoding the machine, without requiring modifications to the basic architecture of the chip, substantially reducing design time. The flexibility of this general purpose architecture enables controllers to be more customized to a particular user's requirements, resulting not only in faster performance by the controller itself, but also in far less reliance on the host's processing power. What could previously only be done by the host in software can now be done by the controller itself much more quickly.

Growing community of inventors

San Jose, CA, United States of America

Anthony J O'Toole