Bell Communications Research, Inc.

Motorola Corporation

Anthony J McAuley

Robert Alan Kempke

Michael P LaMacchia

Paul F Tsuchiya

Daniel V Wilson

A system for a pipeline cascaded content addressable memory CAM system for sequentially processing input data includes an input register, a CAM core, cascade logic and an output register. As the memory association functions produce matches in the CAM core, the cascade logic in parallel composites data associated with each matching CAM core. Each cascade processes a separate data input simultaneously then passes on the cumulative results to the next stage.

Cascadable content addressable memory and system

The present invention encompasses a method of storing ternary data that includes the steps of (1) initializing a conversion register by storing binary-to-ternary mask data in a conversion register; (2) storing ternary data in a content addressable memory (CAM) by inputting a single bit binary data to the conversion register, and converting the binary data into two bits of ternary data using the conversion register; and (3) simultaneously storing the two bits of ternary data in first and second memory cells. For subsequent searching, the method further includes the steps of searching for a match of input search binary data to the stored contents of the CAM; providing a match valid output responsive to the input search binary bits matching any of the stored contents; and generating an address corresponding to a location in the CAM where the match is found.

Ternary CAM memory architecture and methodology

A new class of error detection codes has powerful error detection properties, as well as significant implementation advantages. The inventive error detection codes are used in communication protocols to protect transmitted data from corruption.

Weighted sum codes for error detection

The present invention is generally directed to the transmission of data in various types of communication systems, including local area networks (LANs) and wide area networks (WANs). A main object of the present invention is to provide a system based on a parallel structure that can assemble and disassemble packet information in constant time, no matter how corrupted, out of order, or duplicated the arriving packets. A further object of the present invention is to provide a system that would improve efficiency in broadband networks, particularly if implemented in a VLSI chip using the low complexity architecture-and-reassembly of the present invention.

System for the parallel assembly of data transmissions in a broadband

A switch memory 100 for implementing a multilevel hierarchical routing table in a switch is disclosed. The switch memory 100 includes a plurality of mask circuits 120, 121 and 122, which each correspond to one level of the multilevel hierarchy. Each mask circuit 120, 121 and 122 receives a destination address of an incoming call or packet and masks out portions of the received destination address which do not correspond to the level of the hierarchy with which the mask circuit 120, 121 or 122 is associated. A memory array 130, 131 or 132 corresponding to each mask circuit 120, 121 or 122, is provided which is capable of storing a table of entries including an output port entry and a corresponding destination address of one level of the multilevel hierarchy of destination addresses. Additionally, each memory array 130, 131 or 132 is capable of comparing, in parallel, non-masked portions of the masked destination address outputted from the corresponding mask circuit 120, 121 or 122 with corresponding portions of each destination address of each table entry stored therein. Finally, the switch memory 100 includes a prioritizer 150 for enabling the output of an output port entry of a matched table entry from the memory array 130, 131 or 132, storing destination addresses of the lowest level in the hierarchy, in which a match occurred.

Fast multilevel hierarchical routing table lookup using content

In accordance with an inventive FEC code, data is transmitted in codewords comprising n m-bit symbols. Of the n symbols, k symbols are known information symbols and h symbols are parity symbols for erasure correction. All of the symbols of the codeword are elements of a field of 2.sup.m integers which is closed with respect to addition and multiplication such as a Galois field. To determine the h parity symbols, an encoder circuit derives a matrix corresponding to a set of simultaneous equations in terms of the k known information symbols and the h parity symbols. This set of equations is then solved for the h parity symbols so that a codeword is transmitted comprising k known information symbols and h known parity symbols. At a decoder, the values of up to h erased symbols in the codeword may be reconstructed using a similar set of simultaneous equations.

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Bloomfield, NJ, United States of America

Anthony J McAuley