Texas Instruments Corporation

International Business Machines Corporation

Siemens Aktiengesellschaft

Anthony J Konecni

Girish Anant Dixit

Robert H Havemann

Noel M Russell

Srikanth Bolnedi

John C Forster

Wei-Yung Hsu

Qi-Zhong Hong

Dragan Valentin Podlesnik

Donna Rizzone Cote

Virinder S Grewal

An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate having an interconnecting structure comprised of aluminum, the method comprising the steps of: forming a conductive structure (layers and of FIGS. ) comprised of a metal; forming a dielectric layer (layer of FIGS. ) over the conductive structure, the dielectric layer having an upper surface; forming an opening in the dielectric layer so as to expose a portion of the conductive structure, the opening having sidewalls; selectively depositing an aluminum-containing conductive material (material and of FIG. ) in the opening; and performing an etchback process so as to remove any of the aluminum-containing conductive material formed on the hardmask and so as to etchback any portion of the aluminum-containing conductor which is situated over the upper surface of the dielectric layer. In an alternative embodiment, the method further comprises the step of: forming a hardmask on the upper surface of the dielectric layer, the hardmask having an upper surface and is formed prior to the step of forming an opening in the dielectric layer; and wherein an opening is formed in the hardmask prior to the step of forming an opening in the dielectric layer.

Selective aluminum plug formation and etchback process

A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300&deg; C., and preferably between about 20&deg;-275&deg; C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;< 3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100&deg;-300&deg; C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Low pressure, low temperature, semiconductor gap filling process

An electronic device is provided that compromises a dielectric layer ( ) disposed outwardly from a substrate ( ). The dielectric layer ( ) has at least one contact opening ( ) formed through the dielectric layer ( ). The device has an adhesion layer ( ) disposed outwardly from the exposed surfaces of the dielectric layer ( ) and the substrate ( ). A first barrier layer ( ) is formed outwardly from the adhesion layer ( ). A second barrier layer ( ) is formed outwardly from the first barrier layer ( ). A conductive plug ( ) fills the contact opening ( ) and is disposed outwardly from the second barrier layer ( ).

System and method of forming a tungsten plug

A metallization structure, and associated method, for filling contact and via apertures to significantly reduce the occurrence of microvoids and provide desirable grain orientation and texture. A modified barrier structure is set forth for contact apertures, and a modified liner structure is set forth for via apertures. The metallization fill structure for contact apertures includes a first wetting or glue layer of refractory metal on the contact aperture, a layer of TiN on the first wetting layer, a second wetting layer of plasma-treated refractory metal on the barrier layer, a layer of CVD Al on the second wetting refractory metal layer, and a PVD Al alloy to fill the contact aperture. The fill structure for via apertures includes an initial plasma-treated refractory metal liner deposited on the via aperture. A CVD Al liner is positioned on the initial refractory metal liner. A PVD Al alloy layer is positioned on the CVD Al liner to fill the via aperture.

Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films

A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300&deg; C., and preferably between about 20&deg;-275&deg; C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<&tilde;3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 M Pa, and preferably no more than about 30 M Pa, at temperatures ranging from about 100&deg;-300&deg; C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

A system for constructing semiconductor devices is disclosed. The system comprises a wafer (,) having semiconductor devices (,), a bevel (,), an edge (,), a frontside (,), and a backside (,). The system also has a chamber (,), and a heater (,) coupled to the interior of the chamber (,) and operable to hold and heat the wafer (,). A showerhead (,) is also coupled to the interior of the chamber (,) and is operable to introduce a precursor gas (,) containing copper over the wafer (,). A shield (,) is coupled to the interior of the chamber (,) and is operable to partially shield the bevel (,), the edge (,), and the backside (,) of the wafer (,) from the precursor gas (,). There is an opening (,) in the chamber (,) through which a reactive backside gas (,) may be introduced under the wafer (,). A method for constructing semiconductor devices is disclosed. Step one calls for placing a wafer (,) on a heater (,) in a chamber (,). Step two requires heating the wafer with a heater (,). Step three provides for partially shielding the wafer (,) with a shield (,). In step four, the method provides for introducing a precursor gas (,) containing copper into the chamber (,) above the wafer (,). The last step calls for introducing a reactive backside gas (,) into the chamber (,) below the wafer (,) through an opening (,).

Method and system for constructing semiconductor devices

An electronic device is provided that compromises a dielectric layer (,) disposed outwardly from a substrate (,). The dielectric layer (,) has at least one contact opening (,) formed through the dielectric layer (,). The device has an adhesion layer (,) disposed outwardly from the exposed surfaces of the dielectric layer (,) and the substrate (,). A first barrier layer (,) is formed outwardly from the adhesion layer (,). A second barrier layer (,) is formed outwardly from the first barrier layer (,). A conductive plug (,) fills the contact opening (,) and is disposed outwardly from the second barrier layer (,).

System and method of forming a tungstein plug

A structure and method incorporating a CVD TiN barrier layer 230 over the aluminum plug 220 in order to prevent the high plug resistance caused by the blanket metal film stack 240, 250, and 260 deposition process. Unlike physical vapor deposited (PVD) TiN, CVD TiN 230 does not react with the aluminum 220 during annealing. CVD TiN has also been shown to be a better diffusion barrier for aluminum than PVD TiN. In addition, CVD TiN will disrupt any unfavorable grain boundary propagation through the aluminum plug which may act as a source of electromigration failure. Therefore, the CVD TiN 230 can increase the electromigration resistance, without increasing the contact/via resistance.

CVD tin barrier layer for reduced electromigration of aluminum plugs

An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack. Preferably, the step of forming a first conductor on the liner layer is comprised of depositing an aluminum containing layer using physical vapor deposition. In addition, the step of forming a second conductor on the first conductor is, preferably, comprised of depositing an aluminum containing layer using physical vapor deposition.

PVD deposition process for CVD aluminum liner processing

In a PECVD process, the plasma potential is controlled and maintained at a uniform level to confine the formed plasma to the gap area between the electrodes away from the influence of the walls of the discharge chamber. The plasma potential is controlled by operating the system at a high pressure, above about 12 Torr, and monitoring the operation by observing the DC bias on the upper or driven electrode until a positive potential, preferably greater than about 10V, is developed. At this point a symmetrical glow discharge and a controlled plasma exists between the driven electrode and the susceptor electrode, controllable by maintaining the pressure between about 14 and 20 Torr, to reduce plasma damage to the semiconductor body being coated which maximizes yield.

Process for reducing circuit damage during PECVD in single wafer PECVD

An elemental titanium-free liner and cavity cleansing process is provided that allows for the elimination of conventional sputter etch and elemental titanium depositions. A low power plasma etch provides for pre-conditioning/cleansing of cavities such as contacts and vias. A refractory metal is provided as a cavity liner. Preferably, the liner is comprised of several discrete refractory metal liner layers, each having a thickness of about 25-100 .ANG., that can be applied by CVD and/or PVD. A low power plasma cleanse is preferably interposed between each liner layer deposition. A suitable metal plug can be deposited and directed into the cavity to complete cavity filling. Preferably, the metal plug is an elemental aluminum or aluminum alloy plug that is deposited by CVD and force-filled into the cavity to reduce the incidence of micro-voids within the cavity. Elimination of the conventional sputter etch and the high temperature processing (temp..gtoreq..sup..about. 400.degree. C.) associated with such processing allows for the use of polymeric dielectrics, such as the family of polytetrafluorethylene ('PTFE') compounds, which exhibit a dielectric constant (.kappa.) of about 1.9; parylene (.kappa.=.sup..about. 2.2-2.6); aerogels and xerogels (.kappa.=.sup..about. 1.1-1.8); and the family of polymeric spin-on-glass ('SOG') materials; use of all the foregoing materials being attractive because of the ability of these materials to reduce parasitic capacitance of the interconnects. Because these polymeric materials are temperature sensitive, their use has been limited, as conventional device fabrication practices typically require operation temperatures far in excess of the melting and/or decomposition temperature for these materials.

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Plano, TX, United States of America

Anthony J Konecni