U.S. Philips Corporation

Anthony H Richards

Andreas H Wichern

John D Speake

A radio receiver having a double-balanced mixer stage comprising two pairs of emitter coupled transistors (T,to T,), the common emitters of each pair of transistors being connected to identical current sources (T,, T,and T,). A local oscillator signal is applied differentially to junctions (,) of the base electrodes of the first and fourth transistors (T,, T,) and the second and third transistors (T,, T,), respectively. The rf input signal is applied to the common emitter junctions (,) via damping resistors (R,, R,) which also are connected to respective current sources. Outputs from the pairs of emitter coupled transistors are coupled to cascode stages (,). Further damping resistors (R,, R,) are connected between the differential local oscillator input (,A,,B) and the junctions (,) of the base electrodes. The damping resistors are of a low value typically 25 ohms and serve to stabilize the double-balanced mixer circuit and prevent it from going into oscillation.

Radio receiver with a double-balanced mixer circuit having signal damping elements

A receiver circuit, particularly an integrated, zero IF receiver circuit in which a direct conversion IF stage is separated from an antenna by a further fequency conversion stage which is AC coupled to the direct conversion IF stage. A single crystal oscillator generates a frequency which is multiplied prior to being applied as a local oscillator signal to the further frequency conversion stage and is used to produce another frequency, which is divided to block harmonics, prior to being applied as quadrature related local oscillator signals to the direct conversion IF stage. The direct coversion IF stage includes several dc nulling for compensating for dc offsets.

Receiver circuit

An FSK zero IF receiver has means (DEM) for producing representations of demodulated modulating signals as a series of narrow pulses having a repetition rate greater than the symbol rate of the modulating signals and an adjustable symbol slice demodulator (54 to 66) for determining the data. The demodulator has means for adjusting a symbol slice threshold value in dependence of the pulse like representations of the deviation frequencies which may be different as a result of drifting between the local oscillator and nominal transmitter carrier frequencies (f.sub.L and f.sub.C). The means for adjusting the symbol slice threshold comprises means for measuring the peak excursions of the instantaneous representations of the frequency, the difference between the peak excursions being proportional to the transmitted deviations, means for calculating the mean deviation of the peak excursions, which mean deviation is proportional to the offset between the transmitted center frequency and the local oscillator frequency, and means for setting the symbol slice level to the mean deviation in the case of a 2 level signal or to a plurality of symbol slice levels in the case of a M-ary signal.

Receiver having an adjustable symbol slice demodulator

A d.c. blocking amplifier circuit which has a fast start-up time and can be d.c. coupled to other similar circuits or cascaded with differential amplifiers comprising first and second differential amplifiers (40,42 and 44,46) and first and second balanced input lines (52,56), the first input line (52) being connected to the first differential amplifier which in operation amplifies an a.c. signal applied by way of the first input line (52), and the second input line (56) being connected to the second differential amplifier (44,46) which in operation amplifies an a.c. signal applied by way of the second input line (56). Outputs of the first and second differential amplifiers (40,42 and 44,46) are combined to produce an amplified signal which is independent of the d.c. conditions on each of the first and second balanced signal input lines. The circuit is suitable for use in digital paging receivers which operate a battery economizing regime.

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Cambridge, United Kingdom

Anthony H Richards