International Business Machines Corporation

Kabushiki Kaisha Toshiba

Anthony Gus Aipperspach

Todd Alan Christensen

Gregory John Uhlmann

Derick Gardner Behrends

Peter Thomas Freiburger

Chad Allen Adams

David Howard Allen

Phil Christopher Felice Paone

John Edward Sheets, Ii

David Edward Schmitt

David W Siljenberg

Douglas Michael Dewanz

Louis Bernard Bushard

George Francis Paulik

Nghia Van Phan

Charles Porter Geer

Brian Joy Reed

Kirk David Peterson

David William Boerstler

David Paul Paulsen

Jente Benedict Kuang

Phil Christopher Paone

Paul Allen Ganfield

Jeffrey Douglas Brown

Steven John Baumgartner

Otto M Wagner

Alan P Wagstaff

Jeffrey Milton Scherer

Jesse Daniel Smith

Dennis T Cox

Peder James Paulson

Leland Leslie Day

Joseph Michael Fitzgerald

Toshiaki Kirihata

David Arnold Luick

William Paul Hovis

Dieter F Wendel

Eskinder Hailu

Juergen Pille

Donald W Plass

Sheldon Bernard Levenstein

Fariborz Assaderaghi

Daniel Lawrence Stasiak

John Matthew Safran

Kent Harold Haselhorst

Charles Luther Johnson

David Michael Friend

Salvatore Nicholas Storino

Garrett Stephen Koch

Elizabeth Lair Gerhard

Kerry Christopher Imming

Allan Harvey Dansky

Terrance Wayne Kueper

Steven John Zier

Sebastian Ehrenreich

Pierre B Mollier

Matthew Roger Ellavsky

Gerard Boudon

Michael James Rohn

Morgan D Davis

Ryan Charles Kivimagi

Philip T Wu

Merwin Herscher Alferness

Joseph M Fitzgerald

Binta Minesh Patel

Ieng Ong

Akihiko Fukui

Robert N Krentler

Adrian Zuckerman

Paul W Wong

Biagio Pluchino

Torsten Mahnke

Mark G Veldhuizen

Murali Vaddigiri

Bryan Joe Talik

An integrated circuit (IC) can be configured to provide a managed power distribution to circuits within a plurality of regions of the IC. Each region of the plurality of regions can include a corresponding set of circuits that are electrically connected to a corresponding virtual power island (VPI) within said each region. A global power distribution structure within the IC can be configured to be electrically interconnected to an off-chip voltage supply. The IC can also include a plurality of sets of vertical interconnects (VIs), each set of VIs electrically interconnected to a VPI within a corresponding region. Each set of VIs can also be connected to the global power distribution structure, and can be used to provide a specifically managed voltage through a VPI to a set of circuits within a corresponding region of the IC.

Managed integrated circuit power supply distribution

A system and integrated circuits are provided for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal.

On-chip diagnostic circuitry monitoring multiple cycles of signal samples

A computing system, processing unit, and method are disclosed for detecting a maximum voltage power supply for performing memory testing. The method includes generating, using a sense amplifier of a processing unit and based on a timing of a received pulse signal, first and second drive signals that collectively indicate which of first and second voltages is greater, the first and second voltages produced by respective first and second power supplies. The method also includes coupling, based on the first and second drive signals, the power supply corresponding to the relatively greater voltage of the first and second voltages with the memory.

Detecting maximum voltage between multiple power supplies for memory testing

A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node.

Level-shifting latch

An electrostatic discharge (ESD) protection device to manage leakage current can, in response to a power good (PGOOD) signal, draw the gate terminal of an ESD clamp device to a voltage below ground. The device also drives an inverted copy of the PGOOD signal to a gated inverter, which can inhibit the gated inverter output from drawing the ESD clamp device gate terminal to ground. The ESD protection device also includes the ESD clamp device to, in response to the gate terminal of the ESD clamp device being drawn to a bias voltage less than ground, allow a leakage current to flow through the ESD clamp device that is less than a leakage current allowed to flow in response to the ESD clamp device gate terminal being drawn to ground.

Electrostatic discharge protection device with power management

A method and circuit for implementing enhanced performance dynamic evaluation, and a design structure on which the subject circuit resides are provided. The dynamic evaluation circuit includes a combined precharge and keeper device connected to a precharge node. The dynamic evaluation circuit includes control logic providing a control input to the combined precharge and keeper device. The combined precharge and keeper device responsive to the control input holds the precharge node precharged when the precharge node is not discharged early in an evaluate cycle.

Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeper

A method and elastic buffer circuit are provided for implementing low power, single master-slave elastic buffers in a network chip design to provide a continuous stream of data to multiple sinks from multiple sources, and a design structure on which the subject circuit resides. An elastic buffer only uses a single master-slave register. The circuit includes a finite state machine, and a latch control block (LCB) to implement the single master-slave elastic buffer removing all &#xbd; cycle paths between buffer locations enabling usage of the single master-slave register.

Implementing low power, single master-slave elastic buffer

A method and structures are provided for implementing an integrated circuit with an enhanced wiring structure of mixed double density and high performance wires in a common plane. A wiring structure includes a first wire having a first plane and a first via to a second wire in a second plane having a second via and a third wire having the first plane with height equal to the first wire and the first via, and a third via having a height equal to the second wire and the second via.

Implementing integrated circuit mixed double density and high performance wire structure

A method and circuit for implementing precise eFuse resistance measurement, and a design structure on which the subject circuit resides are provided. An eFuse sense amplifier coupled to an eFuse array and used for current measurements includes balanced odd and even bitlines, and a plurality of programmable reference resistors connected to the balanced odd and even bitlines. First a baseline current measurement is made through one of the programmable reference resistors, and used to identify a network baseline resistance. A current measurement is made for an eFuse path including a selected eFuse and used to identify the resistance of the selected eFuse.

Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistor

Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid '0' and '1' before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a &#x201c;0&#x201d; and &#x201c;1&#x201d;. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem.

Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse

A method and circuit for implementing an eFuse sense amplifier, and a design structure on which the subject circuit resides are provided. A sensing circuit includes a pair of cross-coupled inverters, each formed by a pair of series connected P-channel field effect transistors (PFETs) and an N-channel field effect transistor (NFET). A first pull-up resistor is coupled between a positive voltage supply rail and a first sensing node of the sensing circuit. A second pull-up resistor is coupled between a positive voltage supply rail and a second sensing node of the sensing circuit. A first bitline is coupled to the first sensing node of the sensing circuit and a second bitline coupled to the second sensing node of the sensing circuit. One of a respective reference resistor and a respective eFuse cell is selectively coupled to the first bitline and the second bitline.

Method and circuit for implementing enhanced eFuse sense circuit

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Rochester, MN, United States of America

Anthony Gus Aipperspach