International Business Machines Corporation

Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Globalfoundries Inc.

Infineon Technologies North America Corp.

Jeol Usa, Inc.

Anthony Gene Domenicucci

Yun-Yu Wang

Devendra K Sadana

Stephen W Bedell

Keith E Fogel

Kwong Hon Wong

Horatio Seymour Wildman

Huajie Chen

Lynne Marie Gignac

Kenneth John Giewont

Christian Lavoie

Shreesh Narasimha

Robert H Dennard

Viorel C Ontalus

Karen A Nummy

Paul David Agnello

Terence Lawrence Kane

Richard J Murphy

Effendi Leobandung

Yun Yu Wang

Judson Robert Holt

David Michael Fried

John Gerard Gaudiello

Christopher D Sheraw

Patrick William Dehaven

John Bruley

Glen L Miles

Linda R Black

Neena Garg

Prabhat Tiwari

Craig M Ransom

Kevin K Chan

Dureseti Chidambarrao

Cyril Cabral, Jr

Jack Oon Chu

Ahmet Serkan Ozcan

Qiqing Christine Ouyang

John Albrecht Ott

Viraj Yashawant Sardesai

William Joseph Murphy

Michael John Hargrove

Roy Arthur Carruthers

Oh-Jung Kwon

Christopher Carr Parks

John A Miller

Anda C Mocuta

Jin-Woo Choi

Robert J Purtell

Kam-Leung Lee

Atul Champaklal Ajmera

Junedong Lee

Gerd Pfeiffer

Christine Dehm

Michael Abramovich Gribelyuk

Michael P Tenney

Russell Herbert Arndt

Paul Andrew Ronsheim

Scott W Crowder

Tina Jane Wagner

O Sung Kwon

Stephen Bruce Brodsky

Bradley Paul Jones

Steven H Boettcher

George G Gifford

Michael Joseph MacDonald

Liang-Kai Han

Stephen K Loh

Chung-Ping Eng

Stephen Richard Fox

Frank J Schmidt, Jr

Leon J Kimball

Thomas A Bauer

Judith A Coffin

Masahiro Kawasaki

Jeffrey S McMurray

Terrance M Tornatore

Gregory D Pomarico

Michael E Adamcek

Thomas R Kupiec

Brian E Johnson

Silke H Christianson

A method of fabricating a device using a sequence of annealing processes is provided. More particularly, a logic NFET device fabricated using a low temperature anneal to eliminate dislocation defects, method of fabricating the NFET device and design structure is shown and described. The method includes forming a stress liner over a gate structure and subjecting the gate structure and stress liner to a low temperature anneal process to form a stacking force in single crystalline silicon near the gate structure as a way to memorized the stress effort. The method further includes stripping the stress liner from the gate structure and performing an activation anneal at high temperature on device.

Method of fabricating a device using low temperature anneal processes, a device and design structure

A method of forming a semiconductor device includes implanting an amorphizing species into a crystalline semiconductor substrate, the substrate having a transistor gate structure formed thereupon. Carbon is implanted into amorphized regions of the substrate, with specific implant conditions tailored such that the peak concentration of carbon species coincides with the end of the stacking faults, where the stacking faults are created during the recrystallization anneal. The implanted carbon pins partial dislocations so as to prevent the dislocations from disassociating from the end of the stacking faults and moving to a region in the substrate directly below the transistor gate structure. This removes the defects, which cause device leakage fail.

Reducing dislocation formation in semiconductor devices through targeted carbon implantation

Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.

Relaxed low-defect SGOI for strained SI CMOS applications

A method is provided for forming a metal semiconductor alloy that includes providing a deposition apparatus that includes a platinum source and a nickel source, wherein the platinum source is separate from the nickel source; positioning a substrate having a semiconductor surface in the deposition apparatus; forming a metal alloy on the semiconductor surface, wherein forming the metal alloy comprises a deposition stage in which the platinum source deposits platinum to the semiconductor surface at an initial rate at an initial period that is greater than a final rate at a final period of the deposition stage, and the nickel source deposits nickel to the semiconductor surface; and annealing the metal alloy to react the nickel and platinum with the semiconductor substrate to provide a nickel platinum semiconductor alloy.

Method of silicide formation by adding graded amount of impurity during metal deposition

An integrated circuit is provided including a narrow gate stack having a width less than or equal to 65 nm, including a silicide region comprising Pt segregated in a region of the silicide away from the top surface of the silicide and towards an lower portion defined by a pulldown height of spacers on the sidewalls of the gate conductor. In a preferred embodiment, the spacers are pulled down prior to formation of the silicide. The silicide is first formed by a formation anneal, at a temperature in the range 250&#xb0; C. to 450&#xb0; C. Subsequently, a segregation anneal at a temperature in the range 450&#xb0; C. to 550&#xb0; C. The distribution of the Pt along the vertical length of the silicide layer has a peak Pt concentration within the segregated region, and the segregated Pt region has a width at half the peak Pt concentration that is less than 50% of the distance between the top surface of the silicide layer and the pulldown spacer height.

Structure and method to form a thermally stable silicide in narrow dimension gate stacks

Accordingly, in one embodiment of the invention, a method is provided for reducing stacking faults in an epitaxial semiconductor layer. In accordance with such method, a substrate is provided which includes a first single-crystal semiconductor region including a first semiconductor material, the first semiconductor region having a &#x3c;110&#x3e; crystal orientation. An epitaxial layer including the first semiconductor material is grown on the first semiconductor region, the epitaxial layer having the &#x3c;110&#x3e; crystal orientation. The substrate is then annealed with the epitaxial layer at a temperature greater than 1100 degrees Celsius in an ambient including hydrogen, whereby the step of annealing reduces stacking faults in the epitaxial layer.

Method of reducing stacking faults through annealing

A link portion between a first electrode and a second electrode includes a semiconductor link portion and a metal semiconductor alloy link portion comprising a first metal semiconductor alloy. An electrical pulse converts the entirety of the link portion into a second metal semiconductor alloy having a lower concentration of metal than the first metal semiconductor alloy. Due to the stoichiometric differences between the first and second metal semiconductor alloys, the link portion has a higher resistance after programming than prior to programming. The shift in electrical resistance well controlled, which is advantageously employed to as a programmable precision resistor.

Programmable precision resistor and method of programming the same

Decoder for a stationary switch machine

A high-quality, substantially relaxed SiGe-on-insulator substrate material which may be used as a template for strained Si is described. The substantially relaxed SiGe-on-insulator substrate includes a Si-containing substrate, an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate, and a substantially relaxed SiGe layer present atop the insulating region. The insulating region includes an upper region that is comprised of a thermal oxide and the substantially relaxed SiGe layer has a thickness of about 2000 nm or less.

Defect reduction by oxidation of silicon

A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.

High performance strained silicon FinFETs device and method for forming same

A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230&#xb0; to about 1320&#xb0; C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.

High-quality SGOI by annealing near the alloy melting point

A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 10defects/cm. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.

Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer

A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.

High-quality SGOI by oxidation near the alloy melting temperature

A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 &#x212b;) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.

Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer

Growing community of inventors

New Paltz, NY, United States of America

Anthony Gene Domenicucci