Skyworks Solutions, Inc.

Sige Semiconductor (u.s.), Corp.

Sige Semiconductor, Inc.

The Whitaker Corporation

M/a -com, Inc.

Anthony Francis Quaglietta

Mark M Doherty

Lui Ray Lam

Michael Joseph McPartlin

Joseph A Cuggino

Allen W Hanson

Chun-Wen Paul Huang

Thomas Aaron Winslow

Xuanang Zhu

Jose Harrison

Lui (Ray) Lam

Chen-Wen Paul Huang

Karen R Freitas

Greg Yuen

Kenneth Vern Buer

A circuit comprises an amplifier network including a first amplifier and a second amplifier and a first transistor having a first base. The first transistor is thermally isolated from the second amplifier. The circuit further comprises a second transistor having a second base. The second transistor is thermally linked to the second amplifier. The circuit further comprises coupling circuitry configured to couple the first base to the second base.

Gain compensation circuit

A semiconductor die includes at least one electronic component. an at least partially moisture permeable material disposed on or about the at least one electronic component, at least one opening defining at least one path for moisture to migrate from an environment external to the die into the at least partially moisture permeable material, and a moisture impermeable shield disposed between the at least one electronic component and the at least one opening.

Capacitor metal guard ring for moisture ingression prevention

Peak voltage limiting circuits and method for power amplifiers. A power amplifier and/or a voltage limiting circuit includes a diode circuit coupled to an output of an amplification stage, the diode circuit configured to provide a conductive path from the output when an output voltage exceeds a selected value. The power amplifier and/or voltage limiting circuit also includes a sink circuit coupled to the diode circuit and a bias circuit, the sink circuit configured to reduce a bias voltage provided by the bias circuit when the output voltage exceeds the selected value to thereby limit the output voltage.

Peak voltage limiting circuits and methods for power amplifiers

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections. In some embodiments, a power amplifier (PA) can include a PA die and an amplification stage implemented on the PA die. The amplification stage can include an array of amplification transistors, with the array being configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a sensor implemented on the PA die. The sensor can be positioned relative to the array of amplification transistors to allow sensing of an operating condition representative of at least some of the amplification transistors. The sensor can be substantially isolated from the RF signal.

Devices and methods related to embedded sensors for dynamic error vector magnitude corrections

Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on the packaging substrate, the radio-frequency module including a power amplifier including a bipolar transistor having collector, emitter, base and sub-collector regions, the radio-frequency module further including a conductive via positioned within 35 &#x3bc;m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level, and electrically connecting the radio-frequency module to the packaging substrate using a plurality of connectors.

Fabrication of radio-frequency devices with amplifier voltage limiting features

Provided herein are apparatus and methods for protecting radio frequency (RF) amplifiers from overdrive. In certain configurations, an RF amplification system includes a plurality of RF amplification stages including a first amplification stage and a second amplification stage subsequent to the first amplification stage in a signal path. The first amplification stage includes a first stage field-effect transistor (FET), and the second amplification stage includes a second stage FET and a gate-to-drain feedback circuit electrically connected between a gate and a drain of the second stage FET. The RF amplification system further includes an overdrive detection circuit that senses a drain current of the first stage FET to detect when an overdrive condition is present, and that decreases an impedance of the gate-to-drain feedback circuit in response to detection of the overdrive condition such that a gain of the second stage FET is reduced.

Apparatus and methods for protecting radio frequency amplifiers from overdrive

Disclosed herein are systems and method for voltage clamping in semiconductor circuits using through-silicon via (TSV) positioning. A semiconductor die is disclosed that includes a silicon substrate, a bipolar transistor having collector, emitter, base and sub-collector regions disposed on the substrate, and a through-silicon via (TSV) positioned within 35 &#x3bc;m of the sub-collector region in order to clamp a peak voltage of the bipolar transistor at a voltage limit level.

Amplifier voltage limiting in radio-frequency devices

Provided herein are apparatus and methods for overdrive protection of radio frequency (RF) amplifiers. In certain configurations, an RF amplifier includes a plurality of amplification stages and an overdrive detection circuit. The overdrive detection circuit determines whether or not the RF amplifier is in an overdrive condition based on a current of an input amplification stage. Additionally, when the overdrive detection circuit detects an overdrive condition, the overdrive detection circuit controls an impedance of one or more feedback circuits of one or more amplification stages subsequent to the input amplification stage in a signal path of the RF amplifier to reduce the RF amplifier's gain. The overdrive protection schemes herein can be used to limit large current and voltage swing conditions manifesting within amplification transistors of the RF amplifier.

Apparatus and methods for overdrive protection of radio frequency amplifiers

Amplifier voltage limiting using punch-through effect

A system and method are provided for reducing dynamic EVM of an integrated circuit power amplifier (PA) used for RF communication. In a multistage PA, the largest amplification stage is biased with a high amplitude current pulse upon receipt of a Tx enable, before receipt of the RF signal data burst. The high amplitude current pulse causes a large portion of the total ICQ budget of the multistage PA to pass through the largest amplification stage causing the entire integrated circuit to rapidly approach steady-state operating conditions. A smoothing bias current is applied to the largest amplification stage after the pulse decays to compensate for transient bias current levels while standard bias circuitry is still approaching steady-state temperature.

System and method of prebias for rapid power amplifier response correction

An amplifier is disclosed for providing processing of a variable RF signal, the amplifier comprising a first parallel gain stage and a plurality of second parallel gain stages electrically disposed between an input fixed impedance matching circuit and an output fixed impedance matching circuit. Wherein in operation each of the first parallel gain stage and plurality of second parallel gain stages are for processing the variable RF signal according to at least a characteristic of the RF power or frequency range. Each of the plurality of second parallel gain stages comprising a tunable impedance matching circuit such that when the second parallel gain stage is in operation the tunable impedance matching circuit providing a transformation of impedance to match between the second amplifier and output fixed matching circuit within the frequency range, and other than providing a match within the frequency range when not in operation.

Multiple RF path amplifiers

A novel method and apparatus is disclosed for reducing power dissipation of RF power amplifiers when a reduced output power level is required. The mechanism has the specific purpose of optimizing the collector terminal voltage on portions of the amplifier's RF chain for maintaining linearity while minimizing power consumption. The apparatus permits a smaller DC to DC converter to be used than in prior art, such that it is implemented in the same semiconductor die or module. Furthermore, the invention eliminates the amplification and phase continuity issues that arise from switched state power amplifiers and envelope-following approaches.

Growing community of inventors

Methuen, MA, United States of America

Anthony Francis Quaglietta