Analog Devices,inc.

Analog Devices International Unlimited Company

Anthony E Turvey

Michael E Harrell

Stefano I D'Aquino

Jennifer W Pierdomenico

Murat Demirkan

A clamp circuit comprises an output transistor and a replica transistor coupled as a current minor pair, wherein the replica transistor is scaled in size to the output transistor by a size ratio; a first current source configured to set a current in the replica transistor, wherein the output current is set at a clamped output current value that is a sum of current of the first current source and a scaled value of the current of the first current source determined according to the size ratio; and a register circuit, wherein a register value stored in the register circuit sets the clamped output current value.

Output voltage glitch reduction in test systems

An automated testing system comprises a high side switch circuit coupled to an input/output (I/O) connection, a low side switch circuit coupled to the I/O connection, a high side force amplifier (HFA) coupled to the high side switch, a low side force amplifier (LFA) coupled to the low side switch, an adjusting circuit coupled to the HFA and the LFA, and a control circuit configured to change the adjusting circuit to change control of current at the I/O connection from one of the HFA or LFA to the other of the HFA or LFA.

Output voltage glitch reduction in ate systems

An amplifier circuit comprises a first gain circuit path configured to provide a first signal gain to an input signal, a second gain circuit path configured to provide a second signal gain to an input signal, an auxiliary gain circuit path configured to provide an auxiliary signal gain to an auxiliary input signal, wherein the auxiliary signal gain is equal to the first signal gain minus the second signal gain, a summing circuit configured to sum the second gain signal path and the auxiliary signal path, and logic circuitry configured to change an output of the circuit between the first gain circuit path and the sum of the second gain signal path and the auxiliary signal path, and set the auxiliary input signal equal to the input signal before the changing.

Glitch reduction technique for switched amplifiers having selectable transfer gain

A method and apparatus for driving a current switch with a differential drive signal monitors both the temperature of the switch and the current through the switch. The method and apparatus dynamically control the amplitude of the drive signal as a function of the switch temperature and the current through the switch. The result is a significant reduction in base drive amplitude without compromise to offset and linearity performance of the driver. The resulting dynamic performance of the switch is substantially improved.

Current switch and method of driving the same

Transmission loss compensation is provided for receiver circuits in general, including an ATE receiver circuit having a voltage-to-current converter, such as a transconductance amplifier, that receives a distorted DUT signal and provides an output to a current-to-voltage converter, such as a transimpedance amplifier. The compensation circuit injects a compensation current into the current-to-voltage converter to compensate for transmission losses. The compensation circuit can be configured to inject a plurality of transient compensation currents with different respective time constants and peak values.

Receiver circuit with transmission loss compensation

A common-mode detector includes a first difference amplifier that is connected to compare a first input voltage with a feedback voltage to provide a first result, a second difference amplifier that is connected to compare a second input voltage with the feedback voltage to provide a second result, and a feedback amplifier that is connected to drive the feedback voltage to a level that is substantially the average of the first and second input voltages in response to receiving the first and second results.

Method and apparatus for measuring the common-mode component of a differential signal

A complementary waveform driver is disclosed that generates output signals S,with arbitrary high and low drive states with respect to an independently controlled baseline signal S,. Accordingly, the driver can generate very fast and flexible waveforms with multiple levels and baseline components. The driver implements complementary differential pairs of transistors that alternately source and sink programmable currents to an output port, creating an output waveform with excellent rising and falling edge symmetry, and greatly improved fidelity, especially at low level voltage swings. A complementary amplifier stage defines the baseline voltage level. When combined with a programmable active load and window comparator, the driver is particularly suited for pin electronics in automatic test equipment (ATE) applications.

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Reading, MA, United States of America

Anthony E Turvey