Motorola Corporation

Anthony E Kouvoussis

Michael F Wiles

Thomas H Bennett

Earl F Carlow

Rodney H Orgill

Charles I Peddle

Ernest A Carter

A MOSFET incrementer circuit is disclosed which is adapted for use in conjunction with a clocked register for incrementing the binary value stored within the register. Each stage of the register has an input terminal which is used to determine whether or not the binary value stored in the particular stage is to be toggled. Each of the input terminals is precharged to a high level which corresponds to the no-increment mode of operation. After the input terminals are initially precharged, the input terminal of the least significant stage is driven to a low level to perform an increment. A plurality of series-coupled MOSFET devices are controlled according to output signals provided by each of the register stages for selectively coupling the low level present at the input terminal of the least significant stage to the input terminals of subsequent stages. When a low level is presented to the input terminal of a stage of the register, the binary value stored within the particular stage is toggled when the register is clocked, thereby causing the value stored within the register to be incremented. A common signal is used to initially precharge the voltage at each of the input terminals as well as to select an increment operation.

Incrementer with common precharge enable and carry-in signal

An N-channel field effect transistor microprocessor includes an arithmetic logic unit, a plurality of working registers and address generating circuitry coupled to an internal bus. Control circuitry is coupled to the arithmetic logic unit, the working registers, and the address generating circuitry for producing control signals for controlling operation of the arithmetic logic unit, the working registers, and the address generating circuitry. The microprocessor requires only a single external power supply, and includes means connected to the external power supply for providing electrical energy to the working registers, the arithmetic logic unit, the control circuitry, and the address generating circuitry in order to effect operation thereof.

N-channel field effect transistor integrated circuit microprocessor

A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus. An index register for storing information to be utilized in an indexed addressing mode of operation is coupled to both the first and second sections of the address bus and to the data bus.

Microprocessor having index register coupled to serial-coupled address

Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. The input is coupled to circuitry which inhibits loading of the next instruction to be executed in response to an interrupt request signal applied to the interrupt request input, and also forces a code into the instruction register in response to the interrupt request signal. The code is substantially similar to the code for a software wait instruction or a software interrupt instruction. Therefore, much of the same circuitry within the microprocessor can be used for executing an interrupt operation, a software wait instruction, or a software interrupt instruction.

Microprocessor interrupt logic

A method of generating addresses in a microprocessor includes steps of storing first informationrepresentative of a first address in a first register, such as a program counter register. The first information is transmitted to a first address bus in order to effect addressing the contents of a first location represented by the first address. The first information is also transmitted via the address bus to an incrementor-decrementor circuit. The first information is incremented to produce second information representative of the address of the next instruction during the addressing of the first location. The second information is then transmitted to the first register.

A processor including a first bus, a second bus, and a control circuit for producing control signals includes a counter having a plurality of inputs and outputs responsive to the control circuit and coupled between the first and second buses for incrementing digital information present at the inputs of the counter. The processor includes a first coupling circuit responsive to the control circuit for coupling the counter inputs to the first bus to effect transferring digital information from the first bus to the counter inputs. A second coupling circuit couples the counter inputs to the second bus to transfer digital information from the second bus to the counter inputs in response to the control circuit. A third coupling circuit couples the counter outputs to the second bus to transfer digital information from the counter output to the second bus. When the second and third coupling circuits are both simultaneously activated in response to the control circuit, digital information present at the counter inputs is effectively latched and temporarily stored in the circuit formed by the counter and the second and third coupling circuits. The processor also includes a program register coupled between the first and second buses for temporarily storing digital information received from the counter means by means of a fourth coupling circuit, which operatively couples the outputs of the counter to inputs of the program register to effect transferring digital information from the counter outputs to the program register inputs in response to the control circuit. Fifth and sixth coupling circuits operatively couple the program register outputs to the first or second bus in response to the control circuit to effect transferring digital information from the program register to the first or second buses, respectively.

Processor including incrementor and program register structure

A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus.

Bus switch coupling for series-coupled address bus sections in a

Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. This first input is connected to circuitry which is enabled by a signal from a bit of a condition code register on the microprocessor chip which bit, is set, acts to mask or disenable the interrupt signal, so that the instruction execution operation of the microprocessor chip is not interrupted. A second input of a microprocessor chip is adapted to having a second interrupt signal applied thereto. The second input is connected to other input circuitry which is not enabled by the mask bit of a condition code register. Therefore, the second input acts as a non-maskable interrupt input.

Interrupt circuitry for microprocessor chip

A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed. The address bus is divided into two sections, each N bits wide, one for transferring higher order address bits and the other for independently transferring lower order address bits. This architecture permits execution of many instructions in fewer machine cycles than was previously possible.

Growing community of inventors

Phoenix, AZ, United States of America

Anthony E Kouvoussis