International Business Machines Corporation

Anthony DeGroff Drumm

Louise Helen Trevillyan

Lakshmi Narasimha Reddy

Jagannathan Narasimhan

Brian C Wilson

David James Hathaway

Robert Lowell Kanzelman

Ruchir Puri

Kenneth Wayne Todd

David Shing-Ki Kung

Mark S Fredrickson

Bruce George Rudolph

Peter James Osler

Randall Clay Itskin

Frank Musante

Michael W Dotson

Richard P Abato

Robert F Damiano

Dazhuang J Ma

Charles P Sweet

Marcus Matthew Poplawski

Kathy M McCarthy

Michael K Edwards

Lukas P Van Ginneken

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful.

Task-based multi-process design synthesis

A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also provides result data to the parent process for each candidate object to reduce the overhead of the parent process when performing the transform on the candidate object. The result data, which may include, for example, a set of instructions or hints, may allow a parent process to take advantage of the efforts of the child process in performing the transform.

Task-based multi-process design synthesis with notification of transform signatures

A task-based multi-process design synthesis methodology is reproducible, and relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. Each child process also undoes the transform performed for each object such that the same initial state of the integrated circuit design is used to perform each transform. In addition, the parent process tracks the results of performing the transform by each child process, and applies successful transforms in a controlled sequence.

Task-based multi-process design synthesis with reproducible transforms

In one embodiment, the invention is a method and apparatus for parallel processing of semiconductor chip designs. One embodiment of a method for processing a semiconductor chip design includes flattening a netlist corresponding to the semiconductor chip design, performing logic clustering on one or more logic elements incorporated in the flattened netlist to generate one or more clusters, partitioning the semiconductor chip design in accordance with the one or more clusters, and designing the individual partitions in parallel.

Method and apparatus for parallel processing of semiconductor chip designs

A method and system of designing an electronic circuit includes dividing a chip area of a design into a plurality of bins, identifying a candidate bin in the plurality of bins, and performing an area reduction on the candidate bin.

Method and system for designing an electronic circuit

Computationally efficient methods and systems for optimizing an integrated circuit (IC) design by targeting only a limited subsection of buffer trees in the buffer system for optimization are provided. By making intelligent decisions about which buffer trees to optimize, greater gains in design efficiency (e.g., as measured by reduced delays and/or wire length) may be realized at greatly reduced computational times when compared to conventional techniques that attempt to optimize each buffer tree.

Targeted optimization of buffer-tree logic

An apparatus, program product and method use a congestion relief algorithm in connection with automated buffer insertion to relieve potential congestion during post-layout interconnect routing. The congestion relief algorithm is utilized to manipulate a plurality of L-shaped spans defined in a routing tree, and is configured to apply the congestion relief algorithm to at least a first L-shaped span among the plurality of L-shaped spans by rerouting the first L-shaped span at least partially within a rectangular area bounded by the first L-shaped span.

Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuit

An apparatus, program product and method utilize an interactive request server program to interface a plurality of client computers with a timing analysis program. The interactive request server program receives client requests from the plurality of client computers over a network, and, in response to each client request, accesses the timing analysis program to retrieve timing data based upon such client request and thereafter forwards the timing data to the client computer making such request. The interactive request server program may optionally be implemented using a web server program and an application server program, with the web server program interfacing with the client computers via an Internet-type interface, and the application server program interfacing with the timing analysis program using a programmatic interface supported by the timing analysis program. The web server, program and the application server program interface with one another through the use of scripts, which are executed by the web server in response to client requests, and which generate one or more commands that are issued to the application server program to control the timing analysis program via the programmatic interface.

Interactive client-server environment for performing collaborative timing analysis of circuit designs

A system and method are proposed for estimating interconnect delay in an Integrated Circuit (IC). A formula for effective capacitance is derived which considers the effect of slew as well as resistive shielding of capacitance, thus yielding more accurate delays for both the interconnects and the source driver (transistor gate). In the system and method, a resistor-capacitor (RC) tree model is used for iterative calculations of effective capacitance and slew for each RC tree node. The effective capacitance is determined for each node by proceeding outward from the source to the sinks, and the slew for each node is determined, using the effective capacitances just determined, by proceeding inward from the sinks to the source node. Once the source node slew determined at a previous iteration is within a specified threshold of the source node slew in the present iteration, the method stops and stores the present iteration values as the final estimates.

System and method for fast interconnect delay estimation through iterative refinement

A method for analyzing and optimizing a design, such as a circuit design, which relates to the application of at least one optimization procedure, evaluating the benefit and net cost of the optimization procedure and then through the checkpoint manager, recording and reversing changes of the design. The execution and reversal of multiple optimizations may occur in a trial mode followed by evaluation of the executed and reversed designs and then the reinstatement of the best optimization.

Incremental design tuning and decision mediator

Automatic generation of post-layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints. A new circuit element is assigned a location without determining an allowable physical location on the integrated circuit, and all timing calculations are based on the assigned location. Then, once the timing constraints have been met by one or more new circuit elements, an incremental layout is performed to find physical locations for the new circuit elements, using the assigned locations as initial targets. By using assigned locations during timing calculations and later determining valid physical locations, many different circuit configurations may be evaluated in a short period of time, with only the best ones going through the more time-consuming step of layout and routing.

Method and apparatus for automatic post-layout optimization of an

A simple system and method is disclosed that provides for the identification and removal of unnecessary buffers in a logic circuit. A special pseudo-buffer is added to the library and identified as a buffer cell with zero area. In addition, a feedthrough delay rule is associated with the pseudo-buffer such that it is treated by a timing system as a wire with no delay through which all electrical properties pass. An existing repowering function will then consider the pseudo-buffer as a replacement choice when attempting to select an optimal power level. If the pseudo buffer is chosen, it can be easily removed from the circuit at some time thereafter.

Simplified buffer manipulation using standard repowering function

A system for identifying and bounding the regions of a digital electronic logic design model that are affected by design revisions. The system is useful for improving the efficiency of incremental logic synthesis systems and includes procedures for recording the signals directly affected by user revision operations and for marking signals in the logic to identify those indirectly affected. A smart editor capable of parsing the formal register transfer language (RTL) in which the logic design is described is included in the system.

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Rochester, MN, United States of America

Anthony DeGroff Drumm