Teledyne Wireless, LLC

Gec Plessey Semiconductors, Inc.

Teledyne Defense Electronics, LLC

Teledyne Technologies Incorporated

Celeritek

Anthony David Williams

Richard James Fawley

Gursewak Singh Rai

Husein Masoum

Alex Scarbro

Vincent Lee

Disclosed is a signal generator that includes a memory to store tuning voltage values and offset voltage values. An adder/subtractor circuit is coupled to the memory to produce a sum and a difference of the tuning and offset voltages. A comparator circuit is coupled to the adder/subtractor circuit to receive a digitized voltage controlled oscillator tuning voltage and to compare the digitized voltage controlled oscillator tuning voltage to the sum and difference of the tuning and offset voltages to produce a window bounded by the sum and difference of the tuning and offset voltages. The comparator circuit is further configured to generate control signals. A steering current circuit is coupled to the comparator circuit to receive the control signals from the comparator circuit and to control a steering current based on the control signals.

Digital high speed acquisition system for phase locked loops

A signal generator is disclosed that in one form employs an indirect digital-to-analog converter (DAC) assisted frequency synthesizer for switching a steering current into or out of a phase locked loop (PLL) filter capacitor. The signal generator provides fast switching performance and loop bandwidth adjustment to reduce phase noise and improve phase jitter performance. The signal generator comprises a channel signal selector, a digital-to-analog converter, a window generator circuit, a window comparator, a steering current circuit, a PLL circuit with voltage controlled oscillator (VCO), programmable divider, and a reference oscillator.

High speed acquisition system for phase locked loops

A phase coherent signal generator apparatus is disclosed that outputs a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input to receive a reference clock signal, and outputs to independently supply a master clock signal and a slave clock signal; an accumulating digital synthesizer that includes independent inputs to receive the slave clock signal, a digital frequency tune word signal, a phase tune word signal, and a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes independent inputs to receive the master clock signal and the digital frequency tune word signal, and independent outputs to supply the digital phase tune word signal and the reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal.

Phase disciplined, direct digital synthesizer based, coherent signal generator

A phase coherent signal generator apparatus is disclosed that has fast frequency shifting and numerous phase memory points, outputting a coherent continuous phase signal that includes fast switched multiple different frequency bursts. The apparatus comprises: a clock generator including an input that receives a reference clock signal, an output that supplies a master clock signal, and an output that supplies a slave clock signal; an accumulating digital synthesizer that includes a first input that receives the slave clock signal, a second input that receives a digital frequency tune word signal, a third input that receives a phase tune word signal, a fourth input that receives a reset signal, and an output that supplies a digital coherent continuous phase signal; a master digital synthesizer that includes a first input that receives the master clock signal, a second input that receives the digital frequency tune word signal, a first output that supplies the digital phase tune word signal, and a second output that supplies a reset signal; and a converter that receives the digital coherent continuous phase signal and supplies the coherent continuous phase signal.

A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes an input terminal and an output terminal, a loop filter, a digital phase detector, and an analog phase detector. The digital phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output coupled to the loop filter, the digital phase detector is configured to operate at a first phase comparison frequency. The analog phase detector includes a first input coupled to the input terminal, a second input coupled to the output terminal, and an output alternating current (AC) coupled to the loop filter, the analog phase detector is configured to operate at a second phase comparison frequency. The first phase comparison frequency is different from the second phase comparison frequency.

Noise canceling technique for frequency synthesizer

A frequency synthesizer is disclosed. According to one embodiment, the frequency synthesizer includes a phase locked loop (PLL) having an analog mixer phase detector and an auxiliary digital frequency detector coupled to the phase locked loop. The PLL may include a programmable divider having an input terminal responsive to an output signal of the frequency synthesizer and having an output terminal coupled to an input terminal of the analog mixer phase detector, a loop filter having an input terminal coupled to an output terminal of the analog mixer phase detector, and a voltage controlled oscillator having a control terminal coupled to an output terminal of the loop filter. The programmable divider may include a direct digital synthesizer.

Frequency synthesizer having PLL with an analog phase detector

An apparatus and method for efficiently implementing a satellite transceiver system comprises a digital signal processor for providing input signals to a transmitter, a vector modulator for generating a modulated signal from the input signals, and an output amplifier for amplifying the modulated signal to produce a transmit signal. The invention also includes an attenuator that samples the transmit signal to generate an error signal, a mixer that downconverts the error signal to produce a downconverted error signal, a feedback vector demodulator that demodulates the downconverted error signal to generate result signals that contain error information pertaining to the transmit signal. The digital signal processor may then compare the result signals with the input signals to responsively alter the input signals, and thereby correct for distortion in the transmit signal.

Apparatus and method for efficiently implementing a satellite

A system and method for implementing a cellular radio transmitter device comprises a first oscillator device for generating a first oscillator output signal, a second oscillator device for generating a second oscillator output signal, a power amplifier for amplifying the second oscillator output signal to obtain a transmit signal, a mixer device for combining the first oscillator output signal and the transmit signal to produce a mixer output signal, a phase comparator for comparing the mixer output signal and a transmitter input signal and responsively generating a control signal to control the transmit oscillator, and a feedback path for adding the mixer output signal to the transmitter input signal to compensate for distortion present in the transmit signal.

System and method for implementing a cellular radio transmitter device

A PCMCIA package with a shielded package for radio electronics is inserted into a selected PCMCIA slot with only one edge of the shielded package being immediately accessible. A microwave and radio frequency transparent containment is mounted at a selected edge of the shielded package. An antenna is mounted within the microwave and radio frequency transparent containment for electromagnetic communication through the microwave and radio frequency transparent containment.

Growing community of inventors

Aptos, CA, United States of America

Anthony David Williams