Xilinx, Inc.

Anthony D Williams

Carol A Fields

Jeffrey H Seltzer

Dhimant Patel

Roberta E Fulton

Veena N Kumar

A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that describe the design elements. The functional design elements are linked with selected ones of the documentation elements in the database. A testbench is simulated with the design module, and the generated results are stored in a database and linked with the functional design elements. By linking the simulation results, documentation, and design elements, the characteristics of the design module are easily ascertained by a designer who is reusing the design module.

System and method for assisting in the development and integration of reusable circuit designs

A method and apparatus for developing placement characteristics of a circuit design in conjunction with developing functional aspects of the circuit. In various embodiments, an application programming interface (API) is programmed in a hardware definition language (HDL). The API provides placement directives that can be called from the HDL code that defines functional characteristics of the circuit. The API can also be used in a testbench in order to analyze both the functional and physical placement characteristics of the design. Since the API is programmed in HDL, the placement generated during the implementation phase is the same as the placement analyzed during functional simulation.

Method and apparatus for developing and placing a circuit design

The notion of global signals (e.g., global set/reset and global tristate) is of significance to programmable logic user throughout the design process. Regardless of whether the HDL designer explicitly describes the use of a global signal, they are present in the implemented device since they are an integral part of the initialization and start-up process. This may lead to mismatches between the Register Transfer Level (RTL) simulation and the timing simulation. While a methodology for verifying the functionality of global signals is available for schematic design entry, none exists for HDL design tools. A verification method for HDL designers is disclosed providing access to all the functionality relating to global networks currently available to the schematic designers and allowing reuse of the testbench without losing HDL code portability.

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San Bruno, CA, United States of America

Anthony D Williams