Micron Technology Incorporated

Anthony D Veches

Debra M Bell

James S Rehmeyer

Joshua E Alzheimer

Dale Herber Hiscock

Michael Kaminski

Libo Wang

Di Wu

Brian P Callaway

Walter L Moden

George B Raad

Nathaniel J Meier

Markus H Geiger

William R Stephenson

Stephen Michael Kaminski

Robert Bunnell

Dennis R Blankenship

Scott Eugene Smith

Randall J Rooney

Brett Kenneth Dodds

Dale H Hiscock

This disclosure relates generally to interfaces between memory modules and circuit boards. More specifically, this disclosure relates to interfaces for coupling a memory module to a circuit board such that the memory module is arranged in a plane that is substantially parallel with a plane of the circuit board. Various embodiments disclosed herein include interfaces, memory modules including interfaces or portions of interfaces, and/or circuit boards including interfaces and/or portions of interfaces. Associated devices and systems are also disclosed.

Interfaces for coupling a memory module to a circuit board, and associated devices, modules, and systems

Methods, systems, and devices for techniques for flexible self-refresh of memory arrays are described. A memory system may set a respective refresh region for each respective memory bank of the memory system by tracking access to memory row addresses in respective memory banks used in the respective memory banks. For example, the memory system may monitor respective access commands issued to each respective memory bank and store information in a register of each respective memory bank. The memory system may determine whether a respective memory row address associated with a respective access command is within the respective refresh region and process the respective memory bank. The memory system may update a value stored in a register of the respective memory bank (e.g., a memory row address value) to adjust the refresh region of the respective memory bank without updating refresh regions for other memory banks in the memory system.

Techniques for flexible self-refresh of memory arrays

Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.

Memory with partial array refresh

A memory device comprises multiple memory dice arranged vertically in a stack of memory dice and at least one thermoelectric die contacting the bulk silicon layer of at least one of the memory dice of the multiple memory dice. Each memory die of the multiple memory dice includes an active circuitry layer that includes memory cells of a memory array and a bulk silicon layer. The thermoelectric die is configured to one or both of reduce heat from the memory die when a current is applied to terminals of the thermoelectric die and generate a voltage at the terminals of the thermoelectric die when heat from the memory die is applied to the thermoelectric die.

Power regeneration in a memory device

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled—e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

Semiconductor device with user defined operations and associated methods and systems

Embodiments of the disclosure are drawn to apparatuses, systems, methods, and memories that are capable of performing pattern matching operations within a memory device. The pattern matching operations may be performed on data stored within the memory based on a pattern stored in a register. The result of the pattern matching operation may be provided by the memory. The data on which the pattern matching operation is performed may not be output from the memory during the pattern matching operation.

Apparatuses and methods for on-memory pattern matching

Methods, systems, and devices for voltage regulation distribution for stacked memory are described. A stacked memory device may support various techniques for coupling between voltage regulation circuitry of multiple memory dies, or for coupling of voltage regulation circuitry of some memory dies with circuitry associated with operating memory arrays of other memory dies. In some examples, such techniques may include cross-coupling of voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. In some examples, such techniques may include isolating voltage regulation circuitry based on access activity or a degree of access activity for array circuitry. Dynamic coupling or isolation between voltage regulation circuitry may be supported by various signaling related to a stacked memory device, such as signaling between the stacked memory dies, signaling between a memory die and a central controller, or signaling between the stacked memory device and a host device.

Voltage regulation distribution for stacked memory

Methods, systems, and devices for power distribution for stacked memory are described. A memory die may be configured with one or more conductive paths for providing power to another memory die, where each conductive path may pass through the memory die but may be electrically isolated from circuitry for operating the memory die. Each conductive path may provide an electronic coupling between at least one of a first set of contacts of the memory die (e.g., couplable with a power source) and at least one of a second set of contacts of the memory die (e.g., couplable with another memory die). To support operations of the memory die, a contact of the first set may be coupled with circuitry for operating a memory array of the memory die, and to support operations of another memory die, another contact of the first set may be electrically isolated from the circuitry.

Power distribution for stacked memory

Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

Methods and systems for improving power delivery and signaling in stacked semiconductor devices

Methods, systems, and devices for dynamic power distribution for stacked memory are described. A stacked memory device may include switching components that support dynamic coupling between a shared power source of the memory device and circuitry associated with operating memory arrays of respective memory dies. In some examples, such techniques include coupling a power source with array circuitry based on an access activity or a degree of access activity for the array circuitry. In some examples, such techniques include isolating a power source from array circuitry based on a lack of access activity or a degree of access activity for the array circuitry. The dynamic coupling or isolation may be supported by various signaling of the memory device, such as signaling between memory dies, signaling between a memory die and a central controller, or signaling between the memory device and a host device.

Dynamic power distribution for stacked memory

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a memory device may select an option for a host device to access a memory array including a first portion configured to store user data and a second portion configured to store different data based on whether an ECC function of the memory device is enabled or disabled&#x2014;e.g., storing ECC data when the ECC function is enabled, storing additional user data, metadata, or both when the ECC function is disabled. The host device may disable the ECC function and transmit an input to the memory device as to how to access the memory array. The memory device, based on the input, may select the option for the host device to access the memory array and communicate with the host device in accordance with the selected option.

Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.

Apparatuses and methods for detecting illegal commands and command sequences

Embodiments of the disclosure are drawn to apparatuses, systems, methods for an internet of things (IoT) system to include edge devices that perform at least some functions without communicating with a cloud computing system. An edge device may include a memory with on-memory pattern matching capabilities. The edge device may perform pattern matching operations on data collected by the edge device or sensors in communication with the edge device. Based on results of the pattern matching operations, the edge device may perform various functions, such as transmitting data to the cloud computing system, activating an alarm, and/or changing a frequency at which data is transmitted.

Growing community of inventors

Boise, ID, United States of America

Anthony D Veches