International Business Machines Corporation

Qualcomm Incorporated

Mentor Graphics Corporation

Xilinx, Inc.

Other

Anthony Correale, Jr

Benjamin Bowers

Matthew Wayne Baker

Paul Michael Steinmetz

Irfan Rashid

Francois Ibrahim Atallah

Ruchir Puri

Douglass T Lamb

Nishith Rohatgi

David Shing-Ki Kung

Zhigang Pan

William Goodall, Iii

James Norris Dieffenderfer

Tracey Della Rova

Thomas Anderson Dick

Rajiv V Joshi

Timothy Dooling Sullivan

Douglas Willard Stout

Hazara Singh Rathore

Birendra N Agarwala

Kenichi Tsuchiya

Richard Andre Wachnik

Terry Cain Coughlin, Jr

Nigel G Herron

Robert James Lynch

Eric M Coker

David Wallach

Robert L Goldiez

Philip Michael Iles

Trevor Scott Garner

Terence B Hook

Kerry Bernstein

Robert K Montoye

Richard Gerard Hofmann

Jason D Hibbeler

Thomas Philip Speier

William Robert Reohr

Ahmad R Ansari

William Robert Lee

Geoffrey B Stephens

Stephen M Douglass

Nathaniel Douglas Hieter

Lewis William Dewey, Iii

David M Wu

Rahul K Nadkarni

Peter Dean LaFauci

Michael B Mitchell

Subhrajit Bhattacharya

Eric Thorne

Gregory Christopher Burda

Dennis Charles Wilkerson

Gary T Hendrickson

Veena S Pureswaran

David John Seman

Rahul Krishnakumar Nadkarni

Kim E O'Donnell

Qingqi Wang

Leslie Mark DeBruyne

Nicole Marie Arnold

Sven Eric Meier

Richard M Doney

Ronald William Kohake

Richard Duane Tax

Ketan Vitthal Patel

Les Mark DeBruyne

Gary C Luckett

Erwin A Tate

Andrew Kegl

Charles K Robinson

Waleed K Al-Assadi

Jay Donnelly Grollimund

Brian Thomas Kindl

David W Stout

Wolfgang Friedrich Bultmann

Anthony L Polomik

Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain. In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode.

Power efficient voltage level translator circuit

Aspects disclosed in the detailed description include integrated circuit (IC) design methods using engineering change order (ECO) cell architectures. In particular, exemplary aspects provide a fill algorithm that is both single- and multi-row aware, considers a poly-pitch count, and utilizes metallization of the 'empty space' relative to a suite of available fill cells. The algorithm is also aware of timing critical logic elements and may place ECO fill cells in near proximity to such timing sensitive circuits or other margin critical circuits to allow for decoupling or, if there is a logic error, an ECO cell is placed such that the ECO cell is well positioned to be repurposed as a delay circuit or other function to aid in margin control. For maximum flexibility, the algorithm may also address both pre- and post-route applications.

Integrated circuit (IC) design methods using engineering change order (ECO) cell architectures

Power distribution networks (PDNs) using hybrid grid and pillar arrangements are disclosed. In particular, a process for designing an integrated circuit (IC) considers various design criteria when placing and routing the PDN for the IC. Exemplary design criteria include switching frequencies, current densities, and decoupling capacitance and their impact on temperature. In areas of high localized temperature, a power grid structure is used. In other areas, shared metal track pillars may be used. By mixing power grids with pillars, the IC may reduce local hotspots by allowing the grid to help dissipate heat and assist with decoupling capacitance while at the same time providing pillars in areas of high current density to reduce resistive losses.

Power distribution networks (PDNs) using hybrid grid and pillar arrangements

Disclosed systems and methods pertain to finfet based integrated circuits designed with logic cell architectures which support multiple diffusion regions for n-type and p-type diffusions. Different diffusion regions of each logic cell can have different widths or fin counts. Abutting two logic cells is enabled based on like fin counts for corresponding p-diffusion regions and n-diffusion regions of the two logic cells. Diffusion fills are used at common edges between the two logic cells for extending lengths of diffusion, based on the like fin counts. The logic cell architectures support via redundancy and the ability to selectively control threshold voltages of different logic cells with implant tailoring. Half-row height cells can be interleaved with standard full-row height cells.

Standard cell architecture for diffusion based on fin count

Systems and methods relate to cell placement methodologies for improving length of diffusion of transistors. For example, a first transistor with a first diffusion node which is bounded by a first diffusion cut is identified in a transistor level layout. The first diffusion cut is replaced with a first floating gate, and a first filler cell with a first filler diffusion region is added to extend a length of diffusion of the first diffusion node. Increasing the length of diffusion leads to improving drive strength and performance of the first transistor.

Mitigating length-of-diffusion effect for logic cells and placement thereof

Complementary metal oxide semiconductor (MOS) (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods are disclosed. In one aspect, a CMOS standard cell circuit includes first supply rail, second supply rail, and metal lines disposed in the first metal layer. One or more of the metal lines are dynamically cut corresponding to a first cell boundary and a second cell boundary of the CMOS standard cell such that the metal lines have cut edges corresponding to the first and second cell boundaries. Metal lines not cut corresponding to the first and second cell boundaries can be used to interconnect nodes of the CMOS standard cell circuit. Dynamically cutting the metal lines allows the first metal layer to be used for routing, reducing routing in other metal layers such that fewer vias and metal lines are disposed above the first metal layer.

Complementary metal oxide semiconductor (CMOS) standard cell circuits employing metal lines in a first metal layer used for routing, and related methods

Embodiments that design integrated circuits using a 1&#xd7;N compiler in a closed-loop 1&#xd7;N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1&#xd7;N building blocks. The embodiments may alter elements of the 1&#xd7;N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1&#xd7;N building block elements.

Compiler for closed-loop 1&#xd7;N VLSI design

Compiler for closed-loop 1xN VLSI design

Methods, systems, and media to improve the manufacturability of cells and structures within cells of an integrated circuit are disclosed. Embodiments comprise a method of arranging programmable cells, routing the programmable cells, analyzing the cell arrangement and interconnect wiring for manufacturing improvement opportunities, and modifying the programmable cell structures to incorporate the manufacturing improvements. In some embodiments, wires are spread to prevent shorting. In other embodiments, the reliability of contacts and vias is improved by adding additional metallization to the areas surrounding the contacts and vias, or by adding redundant contacts and vias. In one embodiment, a series of manufacturing improvements are made to integrated circuit cells in an iterative fashion.

Methods, systems, and media to improve manufacturability of semiconductor devices

Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts.

Creating integrated circuit capacitance from gate array structures

Embodiments that create parent-child relationships for reuse of 1&#xd7;N building blocks in a closed-loop 1&#xd7;N system are disclosed. Some methods comprise generating a representation of an IC design, inserting a first 1&#xd7;N building block into the representation, and creating an association between the first 1&#xd7;N building block and a second 1&#xd7;N building block. The association enables the first 1&#xd7;N building block to inherit alterations of attributes of the second 1&#xd7;N building block and enables unique alterations of attributes of the first 1&#xd7;N building block which differ from the second 1&#xd7;N building block. Further embodiments comprise an apparatus having an equivalency determiner to determine a logical equivalence between a two 1&#xd7;N building blocks, an attribute creator that creates a set of attributes and enables one of the 1&#xd7;N building blocks to inherit parent attributes and comprise child attributes.

Uniquification and parent-child constructs for 1xN VLSI design

Embodiments that make DFM alterations to cells of 1&#xd7;N building blocks via a closed-loop 1&#xd7;N compiler are disclosed. Some embodiments comprise using a 1&#xd7;N compiler to detect a relationship between two adjacent cells of a 1&#xd7;N building block. Based on the relationship, the embodiments select a DFM alteration and apply the alteration to a physical design representation. The embodiments may apply various types of DFM alterations depending on the relationship, such as adding polysilicon, adding metal to create redundant connections, and merging diffusion areas to increase capacitance on supply nodes. Further embodiments comprise an apparatus having a cell examiner to examine two adjacent cells of a 1&#xd7;N building block and determine a relationship of the two cells. The apparatus also comprises a DFM selector to select a DFM alteration based on the relationship and a DFM applicator to apply the selected DFM alteration to one of the cells.

Integrated design for manufacturing for 1&#xd7;N VLSI design

Growing community of inventors

Raleigh, NC, United States of America

Anthony Correale, Jr