Other

Freescale Semiconductor,inc.

Nxp Usa, Inc.

Everspin Technologies, Inc.

Anthony Ciancio

Sanjeev Aggarwal

Nicholas David Rizzo

Bernhard Grote

Kenneth H Smith

Brian R Butcher

Kelly Wayne Kyler

Lawrence Scott Klingbeil

Jennifer H Morrison

Mark D Griswold

Fred Reece Clayton

Congyong Zhu

Shrinivas Govindarajan

Amudha R Irudayam

Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a gate electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.

Transistors with source-connected field plates

A method of forming a magnetoelectronic device includes forming a dielectric material () surrounding a magnetic bit (), etching the dielectric material () to define an opening () over the magnetic bit () without exposing the magnetic bit (), the opening () having a sidewall, depositing a blanket layer () of cladding material over the dielectric material (), including over the sidewall, removing by a sputtering process the blanket layer () in the bottom of the opening () and the dielectric material () over the magnetic bit (), and forming a conductive material () within the opening () to form a bit line (). This process reduces errors caused by process irregularities such as edges of the bits () protruding and thereby causing defects in the cladding layer () formed thereover. A bit line or digit line so formed may optionally be tapered at the ends () to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.

Structure and method for fabricating cladded conductive lines in magnetic memories

By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

Semiconductor device and making thereof

An apparatus and method of tungsten via fill using a low pressure, 2-step nucleation tungsten deposition process. The tungsten via fill includes a silane soak, a nucleation film growth, and a bulk tungsten film deposition. The nucleation film growth is a low pressure, 2-step process including a controlled first nucleation film growth and a second nucleation film growth. A wafer fabricating system that includes a film depositing system and a control system is used. The film depositing system includes a reaction chamber with at least one silane-containing gas source, a tungsten-containing gas source, and a substrate heating source. The control system instructs the silane-containing gas source and the tungsten-containing gas source to flow with a significantly higher ratio of silane-containing gas (SiH,) to form a first silane-rich nucleation layer. The control system then instructs the gas sources to flow with a higher ratio of tungsten-containing gas, such as WF,, to form a second tungsten nucleation layer. The low pressure, 2-step process results with improved nucleation film step coverage.

Apparatus and method of a low pressure, two-step nucleation tungsten deposition

Growing community of inventors

Gilbert, AZ, United States of America

Anthony Ciancio