Cadence Design Systems, Inc.

G-2 Networks, Inc.

Anthony Caviglia

Eric Harris Naviasky

William Pierce Evans

Hugh Thompson

Eric Naviasky

Hao Tang

Patrick G Farrell

John Ebner

A time to digital converter with a successive approximation architecture () and a method thereof is provided. The time to digital converter () includes successive approximation analog to digital converter circuitry () configured for converting the differential voltage established in the digital to analog converter () of the successive approximation analog to digital converter circuitry () to a digital representation thereof, where the differential voltage corresponds to a measured time period representing a time difference between receipt of leading edges of two signals. Time to digital converter () may incorporate a current switching unit (') having a plurality of current switching circuits (--) arranged in parallel to increase the precision of digital time output of time to digital converter (). The plurality of current switching circuits (--) can be selectively enabled to alter the sensitivity of the time to digital converter ().

Time to digital converter with successive approximation architecture

A system and method are provided for augmenting frequency tuning resolution in an L-C oscillatory circuit which comprises a source of electrical energy, and a tuned section energized by said source of electrical energy for oscillatory conduction of a resonant current therethrough. The tuned section includes an inductor portion extending in substantially looped manner between first and second connection points to define at least one turn. A primary capacitor portion is connected across at least a primary segment of the conductive member delineated by the first and second connection points. The tuned section further includes a secondary capacitor portion connected across a secondary segment of the conductive member intermediately tapped from the primary segment. The secondary capacitor portion defines a base tuning capacitance for the tuned section, which is down-converted to a fine tuning capacitance when reflected to a calibration capacitance of the primary capacitor portion for adjustable combination therewith.

System and method for augmenting frequency tuning resolution in L-C oscillation circuit

The present disclosure relates to a method, apparatus, and system for locking a phase locked loop (PLL). The method may include receiving a reference signal at a phase locked loop (PLL) circuitry having a first PLL circuitry and a second PLL circuitry. The first PLL circuitry may include a fixed frequency oscillator. The method may further include adjusting a division ratio using, at least in part, a fractional divider circuitry in communication with the fixed frequency oscillator, to generate a feedback signal having a substantially equal frequency and a substantially equal phase in relation to a reference frequency. The method may also include receiving the feedback signal and the reference frequency at a phase detector.

Frequency adjustment in a control system

A clock recovery circuit that can be used for recovering a clock signal from a data stream having a high data rate. The clock recovery circuit has a phase interpolator and non-linear digital to analog converters. These circuits are used to interpolate between the phases produced by a voltage controlled oscillator. A determination to advance or hinder a currently selected phase can be made using an up/down detector, a divider, and control logic. The divider can divide not only the up and down pulses produced by the up/down detector, but also the clock frequency. By dividing the clock frequency, the control logic can be designed using CMOS logic circuits.

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Marriottsville, MD, United States of America

Anthony Caviglia