Intel Corporation

Anthony C Miller

Kannan Raj

Ronald Dean Smith

Oleg B Rashkovskiy

Michael W Rhodehamel

Adrian L Carbine

James A Wilson

Wayne M Needham

Sumeet Agrawal

Scott A Rosenberg

Derek B Feltham

A display device, such as a projector system, may include a plurality of display panels formed from liquid crystal over semiconductor substrates which incorporate not only the pixel elements but memory as well. The presence of memory in the display allows a host system, such as a computer, to send only new picture information to the display and avoid the transmission of information that does not change. Thus, the display update bandwidth required of the host system may be reduced, allowing the host system to use resources typically required by the display update process for improved performance of other operations. In addition, the elimination of redundant information being transmitted to the display may allow more new information to be transmitted, enabling, for example, a higher resolution display.

Liquid crystal over semiconductor display with on-chip storage

A system includes an array of pixel cells, column lines, storage elements and decoding circuitry. The pixel cells are arranged in rows and columns and the column lines are associated with the column pixel cells. The storage elements are associated with a row of the pixel cells. The decoding circuitry is adapted to storage charges on the column lines and after the storage, transfer the charges from the column lines to the storage elements.

Display panel

A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. At least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The measured portion of the semiconductor device is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in the tested portion of the semiconductor device.

Method to perform IDDQ testing in the presence of high background leakage current

A method for IDDQ testing to detect defects in a semiconductor integrated circuit in the presence of a high background leakage current is disclosed. In one embodiment of the present invention at least a portion of the semiconductor device is biased and first, second and third quiescent currents are measured and the currents are then compared. A defect in the circuit will show up as a high quiescent current for one or more of the biasing conditions. In a practical device many test patterns are required, for instance 200 patterns may be necessary to reveal defects. Additionally, the delta in current which is sought to detect the defect may need to be repeated several times to assure its detection.

An electro-optical device may include two pairs of electrodes which apply electric fields oriented at an angle with respect to one another. In this way, a second electric field may be used to create an alignment effect in the electro-optic material which normally is achieved using specially prepared alignment structures. The need for the alignment structures may be reduced or eliminated. The second electric field may be applied, for example, using metallic standoffs which space a top plate from a lower substrate and define a region for the electro-optic material. In this way, in large arrays, the electric field may be applied from a plurality of points improving the uniformity of the applied electric field. In smaller arrays, the field may be applied, for example, using peripheral electrodes.

Aligning electro-optic material having standoffs formed from a fourth or higher metal interconnection layer

An electro-optical device may be defined using metallic standoffs between a top plate and a substrate, such as a silicon substrate in a liquid crystal on silicon (LCOS) technology. In one embodiment, the metallic standoffs may be formed from a metal layer, such as metal four layer, above the metal layer used to form the metal pixel mirrors. In this way, relatively constant and uniform cell thicknesses may be achieved without significantly increasing the processing overhead.

Metallic standoff for an electro-optical device formed from a fourth or higher metal interconnection layer

A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.

Control register bus access through a standardized test access port

A method for detecting open circuits in a semiconductor device, more specifically in a static CMOS device. A device to be tested is powered-up and the clock on the device is stopped so that the device enters a quiescent state. Once the device has reached a quiescent state a first current is measured and after a specified period of time a second current is also measured. The first current and the second current are then compared to determine if there is a defect, i.e. an open circuit, in the device. The determination as to whether or not a device is defective is based upon the difference between the first and second current measurements.

Method for detecting opens through time variant current measurement

A method for IDDQ testing to detect defects in a semiconductor device in the presence of a high background leakage current. In one embodiment at least a portion of a semiconductor device is biased and a first quiescent current measurement is taken. The portion of the semiconductor device that was biased is then unbiased and a second quiescent current measurement is taken. The first and second quiescent currents are then compared to determine if a defect exists in that portion of the semiconductor device.

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Gilbert, AZ, United States of America

Anthony C Miller