Ati Technologies Ulc

Advanced Micro Devices Corporation

Ati Technologies Inc.

Advanced Micro Device, Inc.

Onesta Ip, LLC

Anthony Asaro

Mark Douglas Hummel

Mark Fowler

Kevin B Normoyle

Gongxian Jeffrey Cheng

Michael Mantor

Jeffrey Gongxian Cheng

Benjamin T Sander

Yinan Jiang

Philip Ng

Vydhyanathan Kalyanasundharam

Philip J Rogers

Anirudh Rajendra Acharya

Jimshed B Mirza

Milivoje M Aleksic

Andrew Gregory Kegel

Rex Eldon McCrary

Joseph Lee Greathouse

Carl K Mizuyabu

Alan Dodson Smith

Raymond M Li

Danny H M Cheng

Felix Kuehling

Indra Laksono

Benjamin Tsien

Greggory D Donley

Bryan P Broussard

Wade K Smith

Francisco Leonel Duran

Ahmed M Abdelkhalek

Maggie Chan

Vincent Cueva

Yaniv Adiri

Bo Liu

David Andrew Roberts

Alexander J Branover

Maurice B Steinman

James Raymond Magro

David I J Glen

Kedarnath Balakrishnan

Gordon Caruk

Anthony T Gutierrez

Lu Lu

Paul Blinzer

Robert Scott Hartog

Raja Koduri

Elliot H Mednick

Kostantinos Danny Christidis

Milind Nilkanth Nemlekar

Ruihua Peng

Stephen Patrick Thompson

Amin Farmahini-Farahani

Norman Rubin

Andy Sung

Richard E George

James B Fry

Scott P Murphy

James Doyle

Hari S Thangirala

YuBin Yao

Kathirkamanathan Nadarajah

Ling-Ling Wang

Xiaowei Wang

Kelly Donald Clark Zytaruk

Millind Mittal

Nippon HarshadKumar Raval

Rostyslav Kyrychynskyi

Louis Regniere

Leopold Grinberg

Kevin Normoyle

Sean Keely

Samuel Richard Bayliss

Meenakshi Sundaram Bhaskaran

Sidney D Fortes

Phillip Ng

Xingsheng Wan

Joe Scanlon

David Martinez Nieto

Greggory Douglas Donley

Gordon F Caruk

Michael J Mantor

Kedernath Balakrishnan

Yubin Yao

A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Dynamic memory reconfiguration

Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Dynamic repartition of memory physical address mapping

In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

Extended attributes for shared page tables

A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Memory pools in a memory model for a unified computing system

A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

Method and apparatus for managing memory

Systems, apparatuses, and methods for abstracting tasks in virtual memory identifier (VMID) containers are disclosed. A processor coupled to a memory executes a plurality of concurrent tasks including a first task. Responsive to detecting one or more instructions of the first task which correspond to a first operation, the processor retrieves a first identifier (ID) which is used to uniquely identify the first task, wherein the first ID is transparent to the first task. Then, the processor maps the first ID to a second ID and/or a third ID. The processor completes the first operation by using the second ID and/or the third ID to identify the first task to at least a first data structure. In one implementation, the first operation is a memory access operation and the first data structure is a set of page tables. Also, in one implementation, the second ID identifies a first application of the first task and the third ID identifies a first operating system (OS) of the first task.

VMID as a GPU task container for virtualization

An apparatus includes a graphics processing unit (GPU) and a frame buffer. The frame buffer is coupled to the GPU. Based upon initialization of a virtual function, a plurality of pages are mapped into a virtual frame buffer. The plurality of pages are mapped into the virtual frame buffer by using a graphics input/output memory management unit (GIOMMU) and an associated page table.

Virtualized input/output device local memory management

A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

Access log and address translation log for a processor

A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.

DMA engines configured to perform first portion data transfer commands with a first DMA engine and second portion data transfer commands with second DMA engine

A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

Secure memory access in a virtualized computing environment

A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a plurality of processors. The method includes receiving a memory operation from a processor that references an address in a shared memory, mapping the received memory operation to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

In one form, a memory controller includes a command queue, an arbiter, and a replay queue. The command queue receives and stores memory access requests. The arbiter is coupled to the command queue for providing a sequence of memory commands to a memory channel. The replay queue stores the sequence of memory commands to the memory channel, and continues to store memory access commands that have not yet received responses from the memory channel. When a response indicates a completion of a corresponding memory command without any error, the replay queue removes the corresponding memory command without taking further action. When a response indicates a completion of the corresponding memory command with an error, the replay queue replays at least the corresponding memory command. In another form, a data processing system includes the memory controller, a memory accessing agent, and a memory system to which the memory controller is coupled.

DDR memory error recovery

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Toronto, Canada

Anthony Asaro