Intel Corporation

Anthony A St Amour

Christopher P Auth

Michael L Hattendorf

Oleg Golonzka

Nadia M Rahhal-Orabi

Ajay K Sharma

James S Chung

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

Trench plug hardmask for advanced integrated circuit structure fabrication

Technologies for inverting lithographic patterns are described. In some embodiments the technologies include a method for inverting a lithographic pattern of hole precursors, so as to form one or more high aspect ratio structures on or in a surface of a substrate.

Technologies for inverting lithographic patterns and semiconductor devices including high aspect ratio structures

The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.

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Portland, OR, United States of America

Anthony A St Amour