Martin Marietta Corporation

General Electric Company

Anthony A Immorlica, Jr

Robert J Wojnarowski

Wolfgang Daum

Stanton Earl Weaver, Jr

Bernard Gorowitz

Constantine A Neugebauer

Eric J Wildi

Michael Gdula

Robert F Chase

A high-frequency, high-power, semiconductor device chip is impedance matched to an off-chip impedance by a matching network including a dielectric element located on a substrate ground plane portion adjacent to the device to be matched. A thin film dielectric layer is formed over the dielectric element, the semiconductor device and the surrounding substrate. A patterned metal matching circuit is disposed over the dielectric layer and is in electrical contact with an electrode of the high-frequency, high-power, semiconductor device. An impedance matching network is formed by the patterned metal circuit, the dielectric element, the dielectric layer and the underlying grounded substrate. The matching characteristics of the network can be tailored by selecting suitable dielectric materials for the dielectric element and by altering design of the patterned metal circuit. This fabrication of a high-density-interconnect (HDI) structure provides a method for altering the patterned metal circuit by laser lithography, such that a matching circuit can be uniquely tailored to the individual circuit during manufacture, and eliminating the need to mechanically tune the circuit or stock various versions of metallized substrates.

Off-chip impedance matching utilizing a dielectric element and high

In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

Wafer level integration and testing

The invention relates to the provision of an RF shield for an individual or a collection of integrated circuit chips in a module containing a plurality of hybrid interconnected chips generating interfering RF fields that would interfere with operation of that chip if unshielded. The chips in the module may function in the analog and/or digital mode. The RF shield comprises separate metallizations under and over the chip, the two metallizations being interconnected by a line of discrete electrically conductive vias forming cage-like sides to complete an electrically conductive enclosure about the chip. The vias are spaced closely enough to prevent the escape or entry of RF waves at the frequencies of interest. The RF shield is advantageously fabricated using metallizations and vias that are optically patterned by the same process steps used to effect hybrid interconnection of the chips.

Optically patterned RF shield for an integrated circuit chip for analog

Growing community of inventors

Manlius, NY, United States of America

Anthony A Immorlica, Jr