Synopsys, Inc.

Anshu Malani

Paras Mal Jain

Sudeep Mondal

Rajarshi Mukherjee

A system and method for providing convergence centric coverage for clock domain crossing (CDC) jitter in simulation is described. The method includes, in part, defining one or more design constraints associated with the circuit design, determining at least one group of converging signals associated with the circuit design using the one or more design constraints, applying a multitude of jitters to clock domain crossing (CDC) paths of the at least one group of converging signals, and storing the jitters in a jitter database.

Convergence centric coverage for clock domain crossing (CDC) jitter in simulation

Techniques for verification of integrated circuit design are disclosed. A design relating to an integrated circuit is received (). The design includes a first parameterized element and a second parameterized element (). The first parameterized element is identified as a do-not-care (DNC) element based on usage of the first parameterized element in the design (). A plurality of models relating to the design are generated by a processing device (). A first value of the first parameterized element is not varied during the generating, based on the identification of the first parameterized element as a DNC element (). A second value of the second parameterized element is varied during the generating ().

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Mountain View, CA, United States of America

Anshu Malani