Intel Corporation

Ansheng Liu

Mario J Paniccia

Michael T Morse

Olufemi I Dosunmu

Haisheng Rong

Shlomo Ovadia

John Heck

Remus Nicolaescu

Richard O Jones

Dean Samara-Rubio

Dmitri E Nikonov

Yi Ding

Han-Din Liu

Pradeep Srinivasan

Ling Liao

Graham Trevor Reed

Myung Jin Yim

Andrew Alduino

Wei Qian

Kelly Christopher Magruder

Sungbong Park

Brian H Kim

Alexander Krichevsky

Avi Feshali

Kjetil Johannessen

Harel Frish

Boping Xie

Mark Isenberger

Yimin Kang

Donald L Faw

Meer Nazmus Sakib

Hao Li

Aliasghar Eftekhar

Assia Barkai

Judson D Ryckman

Duanni Huang

Tao Sherry Yin

Lina He

Mengyuan Huang

George A Ghiurcan

Zining Huang

Chi D Chu

David Patel

Peicheng Liao

Seth M Slavin

Yoel Shetrit

Rami Cohen

Hat D Nguyen

Henning Jansen

Michael A Creighton

Kejia Li

Nutan Gautam

Valentin Yepanechnikov

Carsten Brandt

Isako Hoshino

Richard Jones

Embodiments described herein may be related to apparatuses, processes, and techniques related to fully integrated optical coherent modulators on a silicon chip. These coherent modulators may be used to enable transmitters, receivers, transceivers, tunable lasers and other optical or electro-optical devices to be integrated on a silicon chip. In embodiments, the optical coherent modulators may be based on differential microring modulators that may be nested in a Mach-Zehnder Interferometer (MZI) configuration. Embodiments may also be directed to a miniaturized and fully integrated coherent modulators, which can enable terabit per second (Tbps) transceivers in a small form factor based on coherent modulation on a silicon chip. Other embodiments may be described and/or claimed.

Optical coherent transmitter on a silicon chip

An optical modulator includes a substrate, a first dielectric layer over the substrate, a rib waveguide including a PN junction on the first dielectric, a second dielectric layer over the rib waveguide and a stressor layer including a metal, where the first or the second dielectric is between the stressor layer and the PN junction.

Stressed silicon modulator

Embodiments may relate to a wavelength-division multiplexing (WDM) transceiver that has a silicon waveguide layer coupled with a silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may include a tapered portion that is coupled with the silicon nitride waveguide layer. In some embodiments, the silicon waveguide layer may be coupled with a first oxide layer with a first z-height, and the silicon nitride waveguide layer may be coupled with a second oxide layer with a second z-height that is greater than the first z-height. Other embodiments may be described or claimed.

Integrated photonic transceiver

Optical receiver packages and device assemblies that include photodetector (PD) chips having focus lenses monolithically integrated on PD die backsides are disclosed. An example receiver package includes a support structure, a PD die, and an optical input device. The PD die includes a PD, integrated proximate to a first face of the PD die, and further includes a lens, integrated on, or proximate to, an opposite second face. The first face of the PD die faces the support structure, while the second face ('backside') faces the optical input device. The optical receiver architectures described herein may provide an improvement for the optical alignment tolerance issues, especially for high-speed operation in which the active aperture of the PD may have to be very small. Furthermore, architectures described herein advantageously enable integrating a focus lens in a PD die that may be coupled to the support structure in a flip-chip arrangement.

Optical receiver package with backside lens-integrated photodetector die

Embodiments described herein relate to techniques and configurations associated with a photonic apparatus (e.g., PIC) having a photodiode and a bypass capacitor disposed in a channel. In one instance, the apparatus includes a substrate in which at least first and second channels are formed. The first channel includes a first photodiode and a first capacitor coupled to the first photodiode, and the second channel includes a second photodiode and a second capacitor coupled with the second photodiode. The first and second capacitors are provided to assist with biasing the first and second photodiodes respectively and to isolate a signal output by the first and second photodiodes from interference provided by the power supply associated with the apparatus. Additional embodiments can be described and claimed.

Integrated circuit comprising multiple channels with integrated bypass capacitors and photodiodes

Optoelectronic packaging assemblies are provided that are useful for optical data, transfer In high performance computing applications, board to board in data centers, memory to CPU, switch/FPGA (field programmable gate array) for chip to chip interconnects, and memory extension. The packaging assemblies provide fine pitch flip chip interconnects and chip stacking assemblies with good thermo-mechanical reliability. Underfill dams and optical overhang regions and are provided for optical interconnection.

Optoelectronic packaging assemblies

Embodiments of the present disclosure provide an apparatus comprising an integrated circuit with a chip-on-chip and chip-on-substrate configuration. In one instance, the apparatus may include an optical transceiver with an opto-electronic component disposed in a first portion of a die, and a trace coupled with the opto-electronic component and disposed to extend to a surface in a second portion of the die adjacent to the first portion, to provide electrical connection for the integrated circuit and another integrated circuit to be coupled with the second portion of the die in a chip-on-chip configuration. The apparatus may include a second trace disposed in the second portion of the die to extend to the surface in the second portion, to provide electrical connection for the other integrated circuit and a substrate to be coupled with the second portion of the die in a chip-on-substrate configuration. Other embodiments may be described and/or claimed.

Integrated circuit with chip-on-chip and chip-on-substrate configuration

A single hybrid electrical/optical connector simultaneously forms both electrical and optical input/output connections by a single step engagement between elements on a connector and corresponding elements of the opposite gender on a mating connector. The connector can be surface-mounted on a circuit board, and a mating connector can be vertically pluggable onto the connector. The optical elements on the connector and/or the mating connector can be detachable, which can simplify assembly of a system that includes the circuit board. The hybrid electrical/optical connector has applications for optical transceivers. The hybrid electrical/optical connector includes a housing that extends laterally along a housing plane. The housing includes electrical and optical sockets thereon. In some examples, the electrical sockets and the optical sockets are laterally arranged on opposite sides of a division plane perpendicular to the housing plane.

Hybrid electrical/optical connector

A low voltage APD is disposed at an end of a waveguide extending laterally within a silicon device layer of a PIC chip. The APD is disposed over an inverted re-entrant mirror co-located at the end of the waveguide to couple light by internal reflection from the waveguide to an under side of the APD. In exemplary embodiments, a 45&#xb0;-55&#xb0; facet is formed in the silicon device layer by crystallographic etch. In embodiments, the APD includes a silicon multiplication layer, a germanium absorption layer over the multiplication layer, and a plurality of ohmic contacts disposed over the absorption layer. An overlying optically reflective metal film interconnects the plurality of ohmic contacts and returns light transmitted around the ohmic contacts to the absorption layer for greater detector responsivity.

Low voltage avalanche photodiode with re-entrant mirror for silicon based photonic integrated circuits

Embodiments of the present disclosure describe semiconductor substrate techniques and configurations for an optical receiver. In one embodiment, a system includes a semiconductor substrate having one or more optical alignment features formed in a surface of the semiconductor substrate and an optical receiver assembly coupled with the semiconductor substrate, the optical receiver assembly including a photodetector device coupled with the surface of the semiconductor substrate, wherein the one or more optical alignment features facilitate precise optical alignment between a lens assembly and the photodetector device when the lens assembly is coupled with the semiconductor substrate using the one or more optical alignment features. Other embodiments may be described and/or claimed.

Semiconductor substrate for an optical receiver

An integrated optical receiver architecture may be used to couple light between a multi-mode fiber (MMF) and silicon chip which includes integration of a silicon de-multiplexer and a high-speed Ge photo-detector. The proposed architecture may be used for both parallel and wavelength division multiplexing (WDM) based optical links with a data rate of 25 Gb/s and beyond.

Integrated optical receiver architecture for high speed optical I/O applications

Described are embodiments of apparatuses and systems including photonic devices having a conductive shunt layer, and methods for making such apparatuses and systems. A photonic device may include a device substrate, a photo-active region disposed on a first region of the device substrate, an isolation region in the device substrate, a contact disposed on a second region of the substrate such that the isolation region is located between the contact and the photo-active region, and a conductive material overlying the isolation region to shunt the first region with the second region. Other embodiments may be described and/or claimed.

Photonic device with a conductive shunt layer

A semiconductor waveguide based optical receiver is disclosed. An apparatus according to aspects of the present invention includes an absorption region including a first type of semiconductor region proximate to a second type of semiconductor region. The first type of semiconductor is to absorb light in a first range of wavelengths and the second type of semiconductor to absorb light in a second range of wavelengths. A multiplication region is defined proximate to and separate from the absorption region. The multiplication region includes an intrinsic semiconductor region in which there is an electric field to multiply the electrons created in the absorption region.

Germanium/silicon avalanche photodetector with separate absorption and multiplication regions

A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.

Vertical mirror in a silicon photonic circuit

Techniques and architectures for providing a reflective target area of an integrated circuit die assembly. In an embodiment, a reflective bevel surface of a die allows an optical signal to be received from the direction of a side surface of a die assembly for reflection into a photodetector. In another embodiment, one or more grooves in a coupling surface of the die provide respective leverage points for aligning a target area of the bevel surface with a detecting surface of the photodetector.

Apparatus, method and system for providing reflection of an optical signal

Growing community of inventors

Cupertino, CA, United States of America

Ansheng Liu