Teralogic, Inc.

Lsi Logic Corporation

Anoush Khazeni

Gerard K Yeh

David R Auld

Bruce Holmer

Robert Page Gardyne

Meng-Day Yu

The present invention is a method and apparatus to generate an anti-flickered pixel from a source pixel having a source pixel value in a display memory. The apparatus comprises a plurality of storage elements, a filter, a comparator, and an output selector. The plurality of storage elements store a sequence of pixels in the display memory which includes the source pixel. The filter is coupled to the plurality of storage elements to filter the sequence of pixels. The filter generates a filtered pixel corresponding to the source pixel. The comparator is coupled to the plurality of storage elements to compare the source pixel value with a threshold value. The comparator generates a comparison result. The output selector is coupled to the filter and the storage elements to select one of the source and filtered pixels according to the comparison result. The selected one of the source and filtered pixels is the anti-flickered pixel.

Anti-flickering for video display based on pixel luminance

The present invention is a method and apparatus for correcting aspect ratio of a display by scaling a source array of pixel data in a memory by a scale factor to a destination array of pixel data. The apparatus comprises a coefficient unit, a register unit, and an arithmetic unit. The coefficient unit is coupled to a buffer to load N coefficients. The register unit is coupled to the source array to load N pixel data synchronously with the coefficient unit. The N pixel data are started at a location in the source array according to the scale factor. The arithmetic unit is coupled to the coefficient unit and the register unit to perform a filtering operation on the loaded N pixel data using the corresponding N coefficients. The arithmetic unit generates a filtered output corresponding to a scaled pixel in the destination array.

Aspect ratio correction using digital filtering

A system and method for estimating motion vectors between frames of a video sequence which operates with reduced memory loading latency according to the present embodiment. The motion estimation system includes a motion port pixel processing array according to the present embodiment. The processing array includes a reference block memory array for storing a reference block and a candidate block memory array for storing a candidate block. According to the present embodiment, each of the reference block memory array and candidate block memory array are configured with dual ports to a reference block memory and a search window memory. Each of the reference block memory array and candidate block memory array are further configured to allow dual port loading during the entire initialization sequence, when one or more of either a reference block or candidate block is being loaded into the respective memory array. During initialization or loading, memory elements for each of the reference block and candidate block are loaded in parallel according to the present embodiment. This reduces the clock latency of the initial loading of the memory array as well as subsequent loadings of a new candidate block for each column of the search window. This reduces the loading to half the number of cycles as compared with prior art methods. The present embodiment thus efficiently performs motion estimation with reduced memory array loading latency. The processing array of the present embodiment is also capable of operating in either frame mode or field mode.

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Sunnyvale, CA, United States of America

Anoush Khazeni