Qualcomm Incorporated

Anosh Bomi Davierwalla

Aleksandar Miodrag Tasic

Sei Seung Yoon

Dongkyu Park

Cheng Zhong

Chiewcharn Narathong

Mohamed Hassan Abu-Rahma

Klaas Van Zalinge

George Alan Wiley

Gurkanwal Singh Sahota

Bhushan Shanti Asuri

Hari Rao

Chuan Wang

Chinmaya Mishra

Christian Holenstein

Seung-Chul Song

Mehdi Hamidi Sani

James Ian Jaffee

Muhammad Hassan

Vannam Dang

Kashyap Ramachandra Bellur

Berke Cetinoneri

Jusung Kim

Chulkyul Lee

Mohamed Hassan Soliman Abu-Rahma

Chul Kyu Lee

Maziar Hedayati

Aspects of the present relate to reflection type phase shifters for radio frequency (RF) wireless devices. Reflection type phase structures in accordance with aspects described herein can improve device performance with compact configurations, such as where magnetic and capacitive coupling is integrated into a device design to integrate interactions between elements for improved phase shifting performance in a compact design with wideband performance.

Compact low-loss reflection type phase shifter

Omni-band amplifiers support multiple band groups. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes at least one gain transistor and a plurality of cascode transistors for a plurality of band groups. Each band group covers a plurality of bands. The gain transistor(s) receive an input radio frequency (RF) signal. The cascode transistors are coupled to the gain transistor(s) and provide an output RF signal for one of the plurality of band groups. In an exemplary design, the gain transistor(s) include a plurality of gain transistors for the plurality of band groups. One gain transistor and one cascode transistor are enabled to amplify the input RF signal and provide the output RF signal for the selected band group. The gain transistors may be coupled to different taps of a single source degeneration inductor or to different source degeneration inductors.

Omni-band amplifiers

Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes an amplifier circuit, a transformer, and a plurality of downconverters. The amplifier circuit receives and amplifies an input radio frequency (RF) signal and provides an amplified RF signal. The input RF signal includes transmissions sent on multiple carriers at different frequencies to a wireless device. The transformer includes a primary coil coupled to the amplifier circuit and a plurality of secondary coils providing a plurality of output RF signals. The plurality of downconverters downconvert the plurality of output RF signals with a plurality of local oscillator (LO) signals at different frequencies. Each downconverter includes a pair of mixers that receives one output RF signal and one LO signal and provides inphase and quadrature downconverted signals for one set of carriers being received.

Low noise amplifiers with transformer-based signal splitting for carrier aggregation

Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes first and second amplifier circuits and a divert cascode transistor. Each amplifier circuit may include a gain transistor and a cascode transistor. The divert cascode transistor is coupled between the output of the first amplifier circuit and the gain transistor in the second amplifier circuit. The first and second amplifier circuits receive an input radio frequency (RF) signal including transmissions sent on multiple carriers at different frequencies to a wireless device. The first and second amplifier circuits and the divert cascode transistor are controlled to amplify the input RF signal and provide (i) one amplified RF signal for one set of carriers in a first operating mode or (ii) two amplified RF signals for two sets of carriers in a second operating mode.

Low noise amplifiers with cascode divert switch for carrier aggregation

Low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus includes first and second amplifier stages, e.g., for a carrier aggregation (CA) LNA or a multiple-input multiple-output (MIMO) LNA. The first amplifier stage receives and amplifies an input radio frequency (RF) signal and provides a first output RF signal to a first load circuit when the first amplifier stage is enabled. The input RF signal includes transmissions sent on multiple carriers at different frequencies to a wireless device. The second amplifier stage receives and amplifies the input RF signal and provides a second output RF signal to a second load circuit when the second amplifier stage is enabled. Each amplifier stage may include a gain transistor coupled to a cascode transistor.

Low noise amplifiers for carrier aggregation

Multiple-input multiple-output (MIMO) low noise amplifiers (LNAs) supporting carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device, an integrated circuit, etc.) includes a MIMO LNA having a plurality of gain circuits, a drive circuit, and a plurality of load circuits. The gain circuits receive at least one input radio frequency (RF) signal and provide at least one amplified RF signal. Each gain circuit receives and amplifies one input RF signal and provides one amplified RF signal when the gain circuit is enabled. The at least one input RF signal include transmissions sent on multiple carriers at different frequencies to the wireless device. The drive circuit receives the at least one amplified RF signal and provides at least one drive RF signal. The load circuits receive the at least one drive RF signal and provide at least one output RF signal.

Multiple-input multiple-output (MIMO) low noise amplifiers for carrier aggregation

Systems and methods of data transmission are disclosed. In an embodiment, at least two transmitters are selectively activated and at least one transmitter is deactivated at a serial interface to transmit data via at least two distinct lines.

Multiple transmitter system and method

An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.

Systems and methods for producing a predetermined output in a sequential circuit during power on

In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.

Memory device for resistance-based memory applications

A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.

System and method to read and write data a magnetic tunnel junction element

In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.

System and method of pulse generation

Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit. The sense amplifier may generate an output value based on the amplified values received from the output of the magnetic resistance-based memory cell and the reference cell once the sense amplifier receives an enable signal from the digitally-controllable amplifier via the logic circuit.

Digitally-controllable delay for sense amplifier

An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.

Growing community of inventors

San Diego, CA, United States of America

Anosh Bomi Davierwalla