Intel Corporation

Other

Anoop Mukker

Zohar Bogin

Daniel Nemiroff

Karthi R Vadivelu

Satheesh Chellappan

Zhenyu Zhu

Nobuyuki Suzuki

Sridharan Ranganathan

Tuong P Trieu

David W Vogel

Robert J Royer, Jr

Eng Hun Ooi

Brian R Mcfarlane

David J Harriman

Aditya Sreenivas

Suresh Nagarajan

David E Freker

Romesh B Trivedi

Zeeshan Sarwar

Shalini Sharma

Aditya Navale

Mikal Hunsaker

Joseph A Bennett

Shankar Natarajan

Suryaprasad Kareenahalli

Navneet Dour

Ritesh B Trivedi

Ang Li

David Sastry

Adit D Tarmaster

Kuan Hau Tan

Surya Kareenahalli

Dave Freker

Arash Talebi

Wai Ben Lin

Power management circuitry in the solid state drive monitors activity on the plurality of media channels to coordinate an active period and an idle period using credits to manage a power budget for the solid state drive. The power management circuitry to coordinate active and idle periods across components in a workload pipeline in the solid state drive for a given performance target to obtain an optimal power and thermal profile.

Power and thermal management in a solid state drive

Dirty Logical-to-Physical (L2P) entries in an L2P indirection table stored in a host volatile memory buffer are flushed to non-volatile memory in the solid state drive through the use of a write-back mode based on flush checkpoints. The use of write-back mode to flush dirty entries in the L2P indirection table to non-volatile memory in the solid state drive based on flush checkpoints results in an increase in the write bandwidth of the solid state drive.

Host managed buffer to store a logical-to physical address table for a solid state drive

Methods and apparatus for optimizing device power and efficiency based on host-controlled hints prior to low-power entry for PCI Express blocks and components. Data structures containing low-power state capability information mapping one or more fine-grained low-power states for each of at least one of an L0s, L1, L1.1, and L1.2 PCIe-defined low-power state are stored on a PCIe device coupled to a Host via a PCIe link. Messages are exchanged over the PCIe link between the Host and PCIe device to configure, using the low-power state capability information, blocks and/or components on the PCIe device to enter a fine-grained low-power state instead of an associated PCIe-defined low-power state mapped to the fine-grained low-power state when the PCIe device detects a power-change event or receives a command to enter the associated PCIe-defined low-power state. Sequences of power-level changes between multiple fine-grained low-power states may also be implemented.

Method of optimizing device power and efficiency based on host-controlled hints prior to low-power entry for blocks and components on a PCI express device

An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

Method for interface initialization using bus turn-around

An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

The present disclosure provides devices and techniques to dynamically change the operating frequency of an interface where components on the interface have non-common clocks. An interface component may be provided with a frequency negotiation component to negotiate a shift in an operating frequency with other component on an interface where the different components have non-common clocks.

Dynamic adaptive clocking for non-common-clock interfaces

A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

Power control of a memory device through a sideband channel of a memory bus

An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.

Power management of user interfaces with coordinated ultra-low power states

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Configuring a remote M-PHY

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.

Inter-chip communications with link layer interface and protocol adaptor

An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface, wherein the SSIC is configured to issue remote register access protocol (RRAP) commands through a local M-PHY to a remote M-PHY in a low speed burst mode.

Superspeed inter-chip interface

A method and apparatus for dedicating cache entries to certain streams for performance optimization are disclosed. The method according to the present techniques comprises partitioning a cache array into one or more special-purpose entries and one or more general-purpose entries, wherein special-purpose entries are only allocated for one or more streams having a particular stream ID.

Method and apparatus for dedicating cache entries to certain streams for performance optimization

Growing community of inventors

Folsom, CA, United States of America

Anoop Mukker