Imec Vzw

Taiwan Semiconductor Manufacturing Comp. Ltd.

Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Anne Vandooren

Amey Mahadev Walke

Boon Teik Chan

Krishna Kumar Bhuwalka

Anne S Verhulst

Nadine Collaert

Roger Loo

Rita Rooyackers

Naoto Horiguchi

Stefan De Gendt

Daniele Leonelli

A method for forming a stacked field-effect transistor device is provided. The method including: forming a bottom FET device comprising a bottom gate electrode arranged; forming a bonding layer of dielectric bonding material over the bottom FET device; and forming a top FET device on the bonding layer, including: forming a fin structure comprising a channel layer; etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure; forming a dummy gate and a dummy gate spacer layer; forming cuts in the fin structure and the bonding layer pattern; forming recesses underneath a fin structure portion preserved underneath the dummy gate by laterally etching back side surface portions of a bonding layer pattern portion; removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses; removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion; forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity; and forming a gate electrode in the upper and lower gate cavity portions.

Method for forming a stacked FET device

A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

Sequential integration process

A tunnel field-effect transistor (TFET) device is provided comprising a semiconductor substrate and a fin structure disposed thereon. The fin structure comprises a channel region and a source region disposed on the channel region. The TFET further comprises a drain region contacting the channel region, wherein the source region and the drain region are of opposite conductivity type. The TFET also comprises a pocket layer covering a gate interface portion of the source region and contacting at least part of the channel region. The TFET further comprises a gate dielectric layer covering the pocket layer and a gate electrode covering the gate dielectric layer. The gate interface portion of the source region comprises at least three mutually non-coplanar surface segments. A method for manufacturing such a TFET device is also provided.

Tunnel field-effect transistor

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

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Mazy, Belgium

Anne Vandooren