Imec

Katholieke Universiteit Leuven, Ku Leuven R&d

Imec Vzw

Katholieke Universiteit Leuven

K.u. Leuven Research & Development

Anne S Verhulst

Rita Rooyackers

William G Vandenberghe

Wilfried B Vandervorst

Marc Marcel Heyns

Cedric Huyghebaert

Francesca Iacopi

Devin Verreck

Arturo Sibaja-Hernandez

Quentin Smets

Daniele Leonelli

Pol Van Dorpe

Roger Loo

Wim Dehaene

Geoffrey Pourtois

Thomas Hantschel

Stefan De Gendt

Anne Vandooren

AliReza Alian

Kuo-Hsing Kao

A method of operating a pore field-effect transistor (FET) sensor for detecting particles, wherein the pore FET sensor comprises a FET wherein a gate is controlled by a pore filled by a fluid, comprises: controlling a first voltage (V) to set the FET in a subthreshold region; controlling a second voltage (V) to set a voltage difference between the first and second voltages (V) such that an effective difference in gate voltage experienced between a minimum and a maximum effective gate voltage during movement of a particle in the fluid is at least kT/q; and detecting a drain-source current in the FET, wherein the particle passing through the pore modulates the drain-source current for detecting presence of the particle.

Method of operating a pore field-effect transistor sensor for detecting particles

A p-type Tunnel Field-Effect Transistor comprises a drain p-type semiconductor region, a source n-type semiconductor region, and at least one gate stack. The source n-type semiconductor region comprises a lowly doped section with a length of at least 10 nm and with a doping level of n-type dopant elements below 5&#xd7;10at/cmand, in contact with the lowly doped section, a highly doped section with a length between 1 monolayer and 20 nm and with a doping level of n-type dopant elements above 5&#xd7;10at/cm.

Layered structure of a P-TFET

A Tunnel Field-Effect Transistor comprising a source-channel-drain structure, the source-channel-drain structure comprising a source region doped with a dopant element having a first dopant type and a first doping concentration; a drain region doped with a dopant element having a second dopant type opposite compared to the first dopant type, and a second doping concentration, a channel region situated between the source region and the drain region and having an intrinsic doping concentration, or lowly doped concentration being lower than the doping concentration of the source and drain regions, a gate stack comprising a gate electrode on a gate dielectric layer, the gate stack covering at least part of the channel region and extending at the source side up to at least an interface between the source region and the channel region, a drain extension region in the channel region or on top thereof, the drain extension region being formed from a material suitable for creating, and having a length/thickness ratio such that, in use, it creates a charged layer, in the OFF-state of the TFET, with a charge opposite to the charge of the majority carriers in the drain region.

Drain extension region for tunnel FET

A Tunnel Field-Effect Transistor (TFET) device is provided comprising at least one heterosection between the source region and the channel region. The at least one heterosection has a low dielectric constant and thickness below 10 nm. Additionally a pocket region and another heterosection may be added in between the at least one heterosection and the channel region.

Heterosection tunnel field-effect transistor (TFET)

A vertical tunneling field effect transistor (TFET) and method for forming a vertical tunneling field effect transistor (TFET) is disclosed. The vertical tunneling field effect transistor TFET comprises a vertical core region, a vertical source region, a vertical drain region and a gate structure. The vertical core region is extending perpendicularly from a semiconductor substrate, having a top surface, consisting of a doped outer part and a middle part. The vertical source region of semiconducting core material comprises the doped outer part of the vertical core region. The vertical drain region of semiconducting drain material comprises along its longitudinal direction a first drain part and a second drain part, the first drain part either directly surrounding said vertical source region or directly sandwiching said vertical source region between two sub-parts of said first drain part, the second drain part located directly above and in contact with the first drain part. The gate structure comprises a gate dielectric layer directly aside of the first drain part of the vertical drain region and a gate layer directly aside of the gate dielectric layer. The second drain part is extending above the gate layer and gate dielectric layer. The vertical tunneling field effect transistor TFET further comprises a drain contact directly connected to a third drain part, the third drain part being an upper part of the second drain part of the vertical drain region. The vertical tunneling field effect transistor TFET further comprises a source contact electrically connected to the vertical source region. The vertical tunneling field effect transistor TFET further comprises a gate contact electrically connected to the gate layer.

Tunnel field effect transistor and method for making thereof

A Tunnel Field Effect Transistor device (TFET) made of at least following layers: a highly doped drain layer, a highly doped source layer, a channel layer, a gate dielectric layer and a gate electrode layer, the gate dielectric layer extending along the source layer, and a highly doped pocket layer extending in between and along the gate dielectric layer and the source layer, characterized in that the pocket layer extends to between and along the source layer and the channel layer.

Tunnel field effect transistor device and method for making the device

A tunnel Field Effect Transistor is provided comprising an interface between a source and a channel, the source side of this interface being a layer of a first crystalline semiconductor material being substantially uniformly doped with a metal to the solubility level of the metal in the first crystalline material and the channel side of this interface being a layer of this first crystalline semiconductor material doped with this metal, the concentration decreasing towards the channel.

Tunnel field-effect transistor and methods for manufacturing thereof

A tunnel field effect transistor (TFET) and method of making the same is provided. The TFET comprises a source-channel-drain structure and a gate electrode. The source region comprises a first source sub-region which is doped with a first doping profile with a dopant element of a first doping type having a first peak concentration and a second source sub-region close to a source-channel interface which is doped with a second doping profile with a second dopant element with the same doping type as the first dopant element and having a second peak concentration. The second peak concentration of the second doping profile is substantially higher than the maximum doping level of the first doping profile close to an interface between the first and the second source sub-regions.

Line-tunneling tunnel field-effect transistor (TFET) and manufacturing method

A tunnel transistor is provided including a drain, a source and at least a first gate for controlling current between the drain and the source, wherein the first sides of respectively the first and the second gate dielectric material are positioned substantially along and substantially contact respectively the first and the second semiconductor part.

Tunnel transistor, logical gate including the transistor, static random-access memory using the logical gate and method for making such a tunnel transistor

A method to fabricate a hetero-junction in a Tunnel Field Effect Transistor device configuration (e.g. in a segmented nanowire TFET) is provided. A thin transition layer is inserted in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped source region and the lowly doped or undoped channel and allows to contain the whole doping entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Control of tunneling junction in a hetero tunnel field effect transistor

The present disclosure provides a method for manufacturing at least one nanowire Tunnel Field Effect Transistor (TFET) semiconductor device. The method comprises providing a stack comprising a layer of channel material with on top thereof a layer of sacrificial material, removing material from the stack so as to form at least one nanowire from the layer of channel material and the layer of sacrificial material, and replacing the sacrificial material in the at least one nanowire by heterojunction material. A method according to embodiments of the present disclosure is advantageous as it enables easy manufacturing of complementary TFETs.

Method of manufacturing a complementary nanowire tunnel field effect transistor semiconductor device

A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).

Tunnel field-effect transistor with gated tunnel barrier

The present disclosure provides a tunnel field effect transistor (TFET) device comprising at least following segments: a highly doped drain region, a lowly doped up to undoped channel region being in contact with the drain region, the channel region having a longitudinal direction, a highly doped source region in contact with the channel region, the contact between the source region and the channel region forming a source-channel interface, a gate dielectric and a gate electrode covering along the longitudinal direction at least part of the source and channel regions, the gate electrode being situated onto the gate dielectric, not extending beyond the gate dielectric, wherein the effective gate dielectric thickness tof the gate dielectric is smaller at the source-channel interface than above the channel at a distance from the source-channel interface, the increase in effective gate dielectric thickness tbeing obtained by means of at least changing the physical thickness tof the gate dielectric.

Tunnel field effect transistor with improved subthreshold swing

Embodiments of the present disclosure provide a method to fabricate a hetero-junction in a Tunnel Field Effect Transistor (TFET) device configuration (e.g. in a segmented nanowire TFET). Since in prior art devices the highly doped source is in direct contact with the lowly doped or undoped channel, some amount of dopants will diffuse from the source to the channel which cannot be avoided due to the source deposition thermal budget. This out-diffusion reduces the steepness of the doping profile and hence deteriorates the device operation. Particular embodiments comprise the insertion of a thin transition layer in between the source region and channel region such that the out-diffusion is within a very limited region of a few nm, guaranteeing extremely good doping abruptness thanks to the lower diffusion of the dopants in the transition layer. The transition layer avoids the direct contact between the highly doped (e.g. Ge or SiGe) source region and the lowly doped or undoped (e.g. Si) channel and allows to contain the whole doping (e.g. B atoms) entirely within the source region and transition layer. The thickness of the transition layer can be engineered such that the transition layer coincides with the steep transition step from the highly doped source region to the intrinsic region (channel), and hence maximizing the tunneling current.

Method of making a hetero tunnel field effect transistor

A wavelength-sensitive detector is provided that is based on elongate nanostructures, e.g. nanowires. The elongate nanostructures are parallel with respect to a common substrate and they are grouped in at least first and second units of a plurality of parallel elongate nanostructures. The elongate nanostructures are positioned in between a first and second electrode, the first and second electrodes lying respectively in a first and second plane substantially perpendicular to the plane of substrate, whereby all elongate nanostructures in a same photoconductor unit are contacted by the same two electrodes. Circuitry is added to read out electrical signals from the photoconductor units. The electronic density of states of the elongate nanostructures in each unit is different, because the material, of which the elongate nanostructures are made, is different or because the diameter of the elongate nanostructures is different. Each unit of elongate nanostructures therefore gives a different response to incident photons such that wavelength-specific information can be derived with the device.

Growing community of inventors

Houtvenne, Belgium

Anne S Verhulst