Digital Equipment Corporation

Anne S Valiton

David J Sager

Raj K Ramanujan

Jay C Stickney

Joseph Rastegar

This invention is directed to a memory system that determines which blocks of a set of associative blocks in cache memory are unavailable for replacement. This is accomplished by operating the memory system to maintain a duplicate set of tags which track block ownership for this cache pursuant to a 'snoopy' protocol. In addition, the cache system maintains a bit associated with each memory address to indicate whether any data blocks resident in it have been locked. The interlock status of the data blocks in the cache is not communicated to the memory system. Once a block is locked, it cannot be allocated for replacement until it is unlocked. When the cache system encounters a locked block, it skips over that block and allocates the next block of the associative blocks. From this, the memory system infers, by means of a replacement algorithm, that block is being locked and, therefore, cannot be replaced. This enables the memory system to implement an irregular replacement policy for this cache when the block to be replaced is owned and locked.

Data processing system having a data memory interlock coherency scheme

The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.

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Westboro, MA, United States of America

Anne S Valiton